i.MX7Dual ENET cache synchronization?

[sebastianhuber]

Do I have to perform explicit cache synchronization on the i.MX7Dual, e.g. flush transmit buffers and invalidate receive buffers? One of the new features for Cortex-A7 based systems is hardware based cache synchronization for the L2 cache, e.g. AMBA AXI Coherency Extension (ACE). Is this extension present on the i.MX7Dual? I found little documentation to the L2 cache in the user manual.

[sebastianhuber]

It would be nice to mention this lacking feature somewhere in the documentation. Cache synchronization in hardware is a standard feature of the PowerPC based communication processors from Freescale/NXP. I am a bit surprised that we have to perform explicit cache synchronization on this platform.

[igorpadykov · Accepted solution]

Hi Sebastian

for specific features which are implemented in i.MX7D please look at Chapter 4

ARM Platform and Debug i.MX7D Reference Manual, look for features for Cortex-A7, cache.

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

I am afraid this is not implemented in i.MX7.

Best regards
igor
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