i.MX7D Sabre: how to assert the PMIC standby signal in Deep Sleep Mode?

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i.MX7D Sabre: how to assert the PMIC standby signal in Deep Sleep Mode?

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vijayraisinghan
Contributor II

I am working on the i.MX7D Sabre reference board, trying to get the PMIC_STBY_REQ signal to assert to the PMIC when my suspend sequence is initiated. My suspend process programs the GPC/SMC controller to bring the A7 cores into STOP mode and the rest of the system into DSM; however, when WFI is executed and the SMC is doing its power down sequence, the PMIC_STBY_REQ signal is never asserted to the PMIC.

The GPC has been programmed to put both cores into STOP mode, DSM is enabled, VSTBY is enabled, and the power down sequence is programmed for CORE0/Mega-Fast Mix/SCU in Slot 0-2. The caches are then flushed and disabled, the memory is put into self-refresh, and then WFI is executed. According to the TRM, the PMIC_STBY_REQ signal should be asserted, but it is not for me. My suspend code loosely mimics the Linux kernel's suspend code.

Are there any other settings other than configuring the GPC/PGC and then entering DSM required in order for the CCM to assert the PMIC_STBY_REQ signal? For example, is it required that all of the peripheral clocks be gated, is it required for the M4 to be idle, is it required for the oscillator to be powered off, etc?

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Please refer to the following thread, hope it helps:

https://community.nxp.com/message/881464 


Have a great day,
Yuri

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vijayraisinghan
Contributor II

Hello Yuri,

I downloaded the reference manual from the thread you mentioned and verified section 5.5.4.4 requirements. From what I can tell, all of the requirements in that section are being met:

1. LPM0 and LPM1 bits in the GPC_LPCR_A7_BSC must be set to WAIT/STOP (I verified STOP is programmed correctly)

2. The three WFI signals wfi_core0, wfi_core1, and wfi_scu must be signalled in order to go to LPM (I verified that the GPC_LPCR_A7_BSC[MASK_n_WFI] bits are NOT being masked, so these wfi signals should be asserted)

3. If the GPC_LPCR_A7_AD[EN_C0_WFI_PDN] or [EN_C1_WFI_PDN] bits are set, then the LPM trigger condition changes (I verified these bits are not set so we are not using RUN mode signalling)

4. The system will go to DSM when both the A7 and M4 are programmed for STOP mode (I verified that both core0/core1 and M4 LPM bits are set to 0x2 STOP mode)

5. The GPC_SLPCR[EN_A7_FASTWUP_STOP_MODE] and [EN_M4_FASTWUP_STOP_MODE] bits are NOT set (verified not set)

6. The GPC_SLPCR[EN_DSM] bits are set (verified that DSM mode bits are set)

My code then puts the RAM into self refresh and executes WFI. However, I still cannot see the PMIC_STBY_REQ signal being asserted. Below is a register dump of the important registers:

PID:00400002 TID:01860022 Dump GPC registers.
PID:00400002 TID:01860022 GPC_LPCR_A7_BSC = 0xa
PID:00400002 TID:01860022 GPC_LPCR_A7_AD = 0x10a1a
PID:00400002 TID:01860022 GPC_LPCR_M4 = 0x2
PID:00400002 TID:01860022 GPC_SLPCR = 0xe000ffa7
PID:00400002 TID:01860022 GPC_MLPCR = 0x1010100
PID:00400002 TID:01860022 GPC_PGC_ACK_SEL_A7 = 0x10004
PID:00400002 TID:01860022 SLT_CFG0 = 0x45
PID:00400002 TID:01860022 SLT_CFG1 = 0x10
PID:00400002 TID:01860022 SLT_CFG2 = 0x80
PID:00400002 TID:01860022 SLT_CFG3 = 0x20
PID:00400002 TID:01860022 SLT_CFG4 = 0x2
PID:00400002 TID:01860022 SLT_CFG5 = 0x0
PID:00400002 TID:01860022 SLT_CFG6 = 0x0
PID:00400002 TID:01860022 SLT_CFG7 = 0x0
PID:00400002 TID:01860022 SLT_CFG8 = 0x0
PID:00400002 TID:01860022 SLT_CFG9 = 0x0
PID:00400002 TID:01860022 GPC_PGC_CPU_MAPPING = 0x1
PID:00400002 TID:01860022 GPC_PGC_A7CORE0_CTRL = 0x1
PID:00400002 TID:01860022 GPC_PGC_A7CORE1_CTRL = 0x1
PID:00400002 TID:01860022 GPC_PGC_A7SCU_CTRL = 0x6040203
PID:00400002 TID:01860022 GPC_PGC_SCU_AUXSW = 0x511645b
PID:00400002 TID:01860022 FASTMIX PGC register (0xA00?) = 0x1
PID:00400002 TID:01860022 Dump IMR_CORE0/1 registers.
PID:00400002 TID:01860022 GPC_IMR1_CORE0_A7 = 0xfff7ffff
PID:00400002 TID:01860022 GPC_IMR2_CORE0_A7 = 0xffffffff
PID:00400002 TID:01860022 GPC_IMR3_CORE0_A7 = 0xfffffeff
PID:00400002 TID:01860022 GPC_IMR4_CORE0_A7 = 0xffffffff
PID:00400002 TID:01860022 GPC_IMR1_CORE1_A7 = 0xffffffff
PID:00400002 TID:01860022 GPC_IMR2_CORE1_A7 = 0xffffffff
PID:00400002 TID:01860022 GPC_IMR3_CORE1_A7 = 0xffffffff
PID:00400002 TID:01860022 GPC_IMR4_CORE1_A7 = 0xffffffff

My wake up source is the FUNC1 gpio button, which should be the irq 71 set in IMR3. What else is required in order to properly assert the PMIC_REQ_STBY signal?

Thanks!

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