i.MX7D GPIO00 behavior when booting up

[frankyhsu]

Hi Support,

We use GPIO00 as the MR function source of the reset IC, the Saber board has the same connection. We found that the GPIO00 level will be pulled low immediately when the reset is de-asserted. It will cause the reset IC to be asserted to low again and cycle to cycle. At that stage, the bootloader is not started yet and should be controlled by internal ROM.We see the Saber board use a 1uF to isolate the GPIO and MR input and we connect the GPIO to MR directly. It seems NXP has already found this issue? How to solve this issue if we connect to MR directly?

[igorpadykov]

Hi Franky

you are right, i.MX7D Sabre board (SPF-28590.pdf, p23) uses a 1uF (C382) to isolate the GPIO and MR input (U37 TPS3808), it can not be connected to MR directly as this vioaltes power up sequence.

According to sect.4.1.11 Power supplies usage i.MX7D Datasheet:

I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This
can cause internal latch-up and malfunctions due to reverse current flows.

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX7DCEC.pdf

With direct connection to MR unpowered processor GPIO (GWDOG_RST_B) will be driven by VSNVS though R279,
this violates power-up sequence and also this will discharge VSNVS (coincell).

Best regards
igor
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