i.MX7D 24MHz clock output to CCM_CLK1_P pin

[rasmusrahunen]

Hi,

I'm trying to enable 24MHz clock output to i.MX7D CCM_CLK1_P output pin (pin id = Y2). It is going to be used as reference clock to OV5640 camera sensor module. We are using Linux Yocto environment and I would like to know if it is possible to configure this somehow in Linux device tree.

I was already able to get the clock working by hard-coding / direct register write to CCM_ANALOG_CLK_MISC0n register (address 0x30360170). When LVDS1_CLK_SEL field is set to 0x15 and LVDSCLK1_OBEN bit is set to 1, the 24MHz clock appears at CCM_CLK1_P pin.

But I would assume there is a better and cleaner approach to achieve this. Is it possible to enable 24MHz clock to this pin by making configuration changes to Linux device tree only?

I've seen the IMX7D_LVDS1_OUT_SEL and IMX7D_LVDS1_OUT_CLK clocks in imx7d-clock.h file, which could be referenced from the device tree. But I don't know how to make the necessary configuration change.

This is how the device tree entry for the OV5640 sensor looks like now, I suspect that the "clocks" entry should be changed somehow perhaps by setting it to IMX7D_LVDS1_OUT_CLK. But how can I adjust the IMX7D_LVDS1_OUT_SEL field so that 24MHz gets selected?:

    ov5640_mipi: ov5640_mipi@3c {
        compatible = "ovti,ov5640_mipi";
        reg = <0x3c>;
        clocks = <&clks IMX7D_CLK_DUMMY>;
        clock-names = "csi_mclk";

        csi_id = <0>;
        pwn-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
        AVDD-supply = <&vgen6_reg>;
        mclk = <24000000>;
        mclk_source = <0>;
        port {
            ov5640_mipi_ep: endpoint {
                remote-endpoint = <&mipi_sensor_ep>;
            };
        };
    };

Any advice on this? Is it possible via device tree, or do I need to handle this in code?

Best regards,

Rasmus Rahunen

[igorpadykov · Accepted solution]

Hi Rasmus

one can check available clock options in clk-imx7d.c

linux-2.6-imx.git - Freescale i.MX Linux Tree 

linux/include/dt-bindings/clock/imx7d-clock.h

use assigned-clocks,  assigned-clock-parents dts properties described in clock-bindings.txt

linux-2.6-imx.git - Freescale i.MX Linux Tree 

Best regards
igor
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[rasmusrahunen]

Hi Igor,

Thank you for this advice. I managed to get it working with your help!

Here is the device tree node for the OV5640, I've highlighted the important changes in red color:

ov5640_mipi: ov5640_mipi@3c {
    compatible = "ovti,ov5640_mipi";
    reg = <0x3c>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_camera>;
    clocks = <&clks IMX7D_LVDS1_OUT_CLK>;
    clock-names = "csi_mclk";
    assigned-clocks = <&clks IMX7D_LVDS1_OUT_SEL>, <&clks IMX7D_OSC_24M_CLK>;
    assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
    csi_id = <0>;
    pwn-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
    AVDD-supply = <&vgen6_reg>;
    mclk = <24000000>;
    mclk_source = <0>;
    port {
        ov5640_mipi_ep: endpoint {
            remote-endpoint = <&mipi_sensor_ep>;
        };
    };
};

In addition I had to make one small tweak to the arch/arm/mach-imx/clk-imx7d.c file. By default it doesn't support all available clock output options that are defined in i.MX7D reference manual for the LVDS1_CLK_SEL field and I had to add a few entries to the lvds1_sel array, so that the 24MHz clock ("osc") is defined in the array index 0x15:

static const char *lvds1_sel[] = { "pll_arm_main_clk",
    "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
    "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
    "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
    "pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
    "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
    "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
    "pll_dram_main_clk", "UNDEFINED_CLOCK", "osc" };

With these two changes, the 24MHz clock appears at the CCM_CLK1_P output pin.

Best regards,

Rasmus