i.MX7 Reset/Power-up from SVNS without button

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i.MX7 Reset/Power-up from SVNS without button

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jonas_pfaff
Contributor I

Hi,

We are developing a board based on the i.MX7D Sabre and have two questions regarding reset/power up and power down.

1) According to the reference manual of the i.MX7D on pages 1047 and 1048 there are two reset schemes. One with internal and one with external PMIC. How are we supposed to configure the CPU such that it knows that we want to use the external one?

Our goal is to use a backup battery, therefore the CPU would be in SNVS Mode. As soon as external power is applied the CPU should turn on, without the need of an ONOFF Button. In my understanding the PMIC_ON_REQ is normally asserted LOW in SNVS Mode, is that correct? As long as the CPU keeps PMIC_ON_REQ low it is not possible to enable it externally. Then the only way is see to initiate boot-up with external circuitry is to disconnect PMIC_ON_REQ and use the external signal instead.

2) What happens when power is removed, without a "nice" software powerdown? Does the CPU enter SNVS Mode anyway?

Thank you.

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art
NXP Employee
NXP Employee

The Smart PMIC mode implies that the external PMIC's power on logic is edge (not level) sensitive, so, to switch an external PMIC on, the processor's SNVS logic generates a High level pulse (not constant level signal). This mode is not practically implementable with the PF series PMICs since their power on logic is level sensitive.

The possible option to switch the PMIC On when the main power is applied without disconnecting the PMIC_ON_REQ signal from PMIC is to generate a tamper event once the main power is applied (tamper event is one of the power on events). The possible implementation is as follows. Typically, all TAMPER pins are pulled up to VDD_SNVS_1P8_CAP. It is possible to add a single FET to pull one of these pins to Low when main power is applied.

Another possible option is to add a simple circuit that generates a Low pulse on the ONOFF pin when the main power is applied.

Best Regards,

Artur

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art
NXP Employee
NXP Employee

Q. How are we supposed to configure the CPU such that it knows that we want to use the external one?

A. No special configuration is required since in both cases PMIC_ON_REQ operates as the Main Power On signal.

The PMIC_ON_REQ signal operation logic is as follows. When applying the VDD_SNVS_IN voltage, PMIC_ON_REQ goes High, so, after that, when the main power is applied, external PMIC immediately starts up and applies the power to the processor, that starts running. Then, from the Run mode, PMIC_ON_REQ can be switched to Low in software, that turns the main power Off. Assuming that the VDD_SNVS_IN voltage is still in place, from this state the processor can be awaken back up by the ONOFF button, RTC alarm event (RTC runs in the SNVS power domain), or Tamper event. All these events cause PMIC_ON_REQ to go High, turning the main power on.

Q. What happens when power is removed, without a "nice" software powerdown? Does the CPU enter SNVS Mode anyway?

A. Assuming that the VDD_SNVS_IN voltage remains in place, the processor goes to the SNVS mode in that case. All its previous state will be lost.


Have a great day,
Artur

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jonas_pfaff
Contributor I

Hi Artur,

Q2 is clear now, thank you for that.

For Q1 we have a follow-up question: If we want to awake the processor while it runs in the SNVS power domain as soon as the main power supply is back without the intervention of the ONOFF button or any other event? According to your description the PMIC_ON_REQ is held Low by the processor and can't therefore be asserted by any external circuit.

We have two possible explanations but are not sure which way to go. 

The Sabre Eval Board has 0 Ohm resistors which can be added or removed to choose if the PMIC_POWRON is connected to the Watchdog or the processor PMIC_ON_REQ. Here we would remove R281 such that only the Watchdog circuit can control the PMIC. This way we lose the possibility to power down the PMIC through the PMIC_ON_REQ signal.

pastedImage_1.png

According to the processor datasheet on the other hand it is possible to choose between dump and smart PMIC by modifying some SNVS registers. If we understand it correctly the smart PMIC mode does not hold down the PMIC_ON_REQ but generates only a short pulse and leaves it up to an external circuit to control the PWRON signal afterwards. Is that correct?

Are both variants feasible? If yes, are there any pros or cons?

Best regards

Jonas

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art
NXP Employee
NXP Employee

The Smart PMIC mode implies that the external PMIC's power on logic is edge (not level) sensitive, so, to switch an external PMIC on, the processor's SNVS logic generates a High level pulse (not constant level signal). This mode is not practically implementable with the PF series PMICs since their power on logic is level sensitive.

The possible option to switch the PMIC On when the main power is applied without disconnecting the PMIC_ON_REQ signal from PMIC is to generate a tamper event once the main power is applied (tamper event is one of the power on events). The possible implementation is as follows. Typically, all TAMPER pins are pulled up to VDD_SNVS_1P8_CAP. It is possible to add a single FET to pull one of these pins to Low when main power is applied.

Another possible option is to add a simple circuit that generates a Low pulse on the ONOFF pin when the main power is applied.

Best Regards,

Artur

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siva_prabhakara
Contributor III

hi @art ,

I am trying the SRTC wakeup on i.MX8M mini from SNVS mode. I did a poweroff and observed that 1.8 and 0.8V SNVS rails are high, after i set rtc alarm wakeup register. But it won't wakeup from SNVS mode. What could be wrong? 

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