i.MX7 DDR Stress Test Tool

[waynekuo]

Hi Experts,

I have a question for DDR Stress Test Tool.
I use DDR Stress Test Tool Ver 2.70.

On i.MX6Q,
After I set the parameters and download the *.inc file, then press the Calibration buttom , if the calibration pass, tool will generate a DDR parameter set to tell me the optimal pararmeter for the testing board. Like:

   MMDC registers updated from calibration

   Write leveling calibration
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00140016
   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0024001F
   MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001B002A
   MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00150026

   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x43240338
   MPDGCTRL1 PHY0 (0x021b0840) = 0x03240318
   MPDGCTRL0 PHY1 (0x021b483c) = 0x43200334
   MPDGCTRL1 PHY1 (0x021b4840) = 0x032C0270

   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x3C2E3230
   MPRDDLCTL PHY1 (0x021b4848) = 0x38363042

   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x323A3E38
   MPWRDLCTL PHY1 (0x021b4850) = 0x46304436

Success: DDR calibration completed!!!

On i.MX7D,
if calibration pass, the tool just show the "Final write delay = 0xXXXXXXXX" and tell me DDR calibration completed. Linke:

   Final write delay = 0x04040404
   -Note: final delay is based on the center of all passing byte lanes

   Success: DDR calibration completed!!!

As my experience, we need to fill the optimal parameters badk into BSP source code.
However, i.MX7 DDR Stress Test Tool does not generate the optimal parameter set that I can used.

Here is my questions:
1. Does DDR Stress Test Tool generate the optimal DDR parameter on i.MX7 serial?
2. If "Final write delay" is the optimal parameter, where should I fill back to source code? Which memory address should I fill?

Best Regards,
Wayne Kuo

[waynekuo]

Hi Yuri,

Here is my understanding, if I'm wrong please correct me.

Cause i.MX6 / i.MX7 DDR controller is different, calibration function on DDR Stress Test Tool is not support for i.MX7 DDR calibration,but stress test function can still work on i.MX7(?).

So i.MXX7 DDR calibration step will be:

1. Fill the i.MX7D DRAM Register Programming Aid and get the DDR register parameters.

2. Use i.MX6/7 DDR Stress Test Tool to do the stress test for this set of register parameters.

3. Use memtester on OS to do the DDR test.

If the above step pass, the DDR register parameters are workable.

However, if the parameters generated by i.MX7D DRAM Register Programming Aid can not pass the stress test, what should I do?

Best Regards,

Wayne Kuo

[Yuri]

Hello,

  Recent DDR Stress tool provide some calibration for i.MX7 too. 

https://community.nxp.com/thread/437875 

Regards,

Yuri.

[jan_spurek · Accepted solution]

Hello Yuri,

just to add some more information:

1.  The recent version of DDR Stress Tester performs Read and Write calibration. Write leveling calibration is not performed due to the above mentioned reason - different memory controller.

2. The DDR Stress Tester then summarizes the results in the following way:

Final write delay = 0x04040404
   -Note: final delay is based on the center of all passing byte lanes

Similar output is also for read calibration.Those values should be used to update the DCD table in the source code. The addressses are: 0x30790030 - DDR_PHY_OFFSET_WR_CON0 (Write Calibration) and 0x30790020 - DDR_PHY_OFFSET_RD_CON0 (Read Calibration). You need to look into the DDR PHY registers (DDRP), not DDRC.

3. Please use the most recent version of the DDR Stress Tester - v2.70. In the earlier versions there is an issue regarding read/write operations for i.MX7.

Best Regards,

Jan

[Yuri]

Hello,

1.

  According to Stress test FAQ :

 ” ... calibration is not supported or needed when using MX7. The reason is, MX7 uses a different memory controller

than the MX6 series. The MX6 series memory controller has built-in support for calibration where the MX7 memory

controller does not.”

   Note, i.MX6 DRAM memory controller is MMDC, bit i.MX7 one - is DDRC. Looking over the i.MX7 Reference Manual,

we can notice, that i.MX7 DDRC supports so called training procedure regarding DQS adjusting : WRITE LEVELING

and GATE LEVELING. But there are no considerations about Read Data Bit Delay Calibration and Write Data Bit Delay Calibration.

  The linked below is the recent i.MX6/7 DDR Stress Test Tool V2.70.

i.MX6/7 DDR Stress Test Tool V2.70 

  As for i.MX7D DRAM Register Programming Aid, please refer to the following :

i.MX7D DRAM Register Programming Aid 

2.

  Please refer to Chapter 1 (Porting U-Boot from an i.MX 6/7 Reference Board to

an i.MX 6/7 Custom Board) of “i.MX_BSP_Porting_Guide.pdf” - regarding memory

initialization for Linux.

Recent BSP :

 https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&Parent_nodeId=13376994810717061... 

Summary page :

i.MX 6 / i.MX 7 Series Software and Development Tool|NXP 

Also, the following may be useful :

Freescale i.MX6 DRAM Port Application Guide-DDR3 

http://www.freescale.com/webapp/Download?colCode=FTF-SDS-F0170 

Have a great day,
Yuri

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