i.MX6solo Gated Mode phase question.

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i.MX6solo Gated Mode phase question.

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Contributor III
37.4.3.6.1 Gated Mode.pngDear community.
Our customer has question below.
In the following figure of 37.4.3.6.1  of i.MX6SDL Reference manual, data reading is done at the falling edge of clock,
Can it be read at the rising edge of clock?
Is there a function to invert the clock latch phase?
Fig1.png
Data sheet of IMX6SDLAEC described on page 94, it is rising edge, which is collect?
Fig2.png
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NXP TechSupport
NXP TechSupport

Hi Takashi

you are right it is rising edge and clock polarity can be changed using CSI0_SENS_PIX_CLK_POL

bit register IPU_CSI0_SENS_CONF, described in 38.5.151 CSI0 Sensor Configuration

Register (IPU_CSI0_SENS_CONF) i.MX6SDL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Best regards
igor
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