i.MX6ULL interrupt table issue?

[felixhsu]

Hi All

Could you explanation the i.MX6ULL interrupt table IRQ number why different between the i.MX6ULLRM rev0 and i.MX6ULLRM rev1?

Thanks.

i.MX6ULL REV0

i.MX6ULLRM REV1

[igorpadykov · Accepted solution]

Hi Felix

interrupt table did not change, changed only representation:

rev.1 did not include offset for 32 interrupts, as described in sect.3.2I.MX6ULL RM

Cortex A7 interrupts The Global Interrupt Controller (GIC) collects up to 128 interrupt requests

from all chip sources and provides an interface to the Cortex A7 CPU. The first 32 interrupts are
private to the CPUs' interface. These interrupts are not included in the table below..

Detailed description of GIC interrupts usage can be found in SDK documentation:

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------