i.MX6ULL Power-Up Sequence

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i.MX6ULL Power-Up Sequence

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mikitakashi
Contributor II

Please tell us about the following points in Power-Up Sequence of i.MX6ULL.

1. IMX6ULLIEC.pdf (DataSheet) has no sequence description for the following power supply. Would you mind thinking that there is no sequence order if it is after VDD_SNVS_IN?
-NVCC_DRAM
-NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD
-VDDA_ADC_3P3,ADC_VREFH

2. Is there any problem with the POWER UP sequence(Step) below? Also, at Step 4, the NVCC (* 1) power supply is still OFF, but can not leak to the NVCC (* 1) power supply terminal (* 2)?
-Step1 : VDD_SNVS_IN (+3.3V)
-Step2 : VDD_HIGH_IN (+3.3V)
-Step3 : VDD_SOC_IN (+1.35V)
-Step4 : NVCC_DRAM (+1.35V)
-Step5 : NVCC(*1) / VDDA_ADC_3P3 / ADC_VREF(+3.3V)
(*1)NVCC : NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD

Thank you.

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mikitakashi
Contributor II

I'm sorry.

The questions duplicated. Please ignore this post.

View solution in original post

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 

 

  The recommended power up sequence of i.MX 6ULL is as following:

 

VDD_SNVS_IN -> VDD_HIGH_IN -> VDD_SOC_IN and all the rest suppliers.

 

  So, You are right, there is no sequence order for NVCC_xxx and VDDA_ADC_3P3, ADC_VREFH.

Your sequence is acceptable. Also, note, the POR_B input must be immediately asserted at power-up

and remain asserted until after the last power rail reaches its working voltage.

 

Have a great day,

Yuri

 

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mikitakashi
Contributor II

Hi Yuri

Thank you

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mikitakashi
Contributor II

I'm sorry.

The questions duplicated. Please ignore this post.

View solution in original post

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196 Views
mikitakashi
Contributor II

Hi Yuri

Thank you very much.

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