i.MX6ULL Power-Up Sequence

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i.MX6ULL Power-Up Sequence

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mikitakashi
Contributor II

Please tell us about the following points in Power-Up Sequence of i.MX6ULL.

1. IMX6ULLIEC.pdf (DataSheet) has no sequence description for the following power supply. Would you mind thinking that there is no sequence order if it is after VDD_SNVS_IN?
-NVCC_DRAM
-NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD
-VDDA_ADC_3P3,ADC_VREFH

2. Is there any problem with the POWER UP sequence(Step) below? Also, at Step 4, the NVCC (* 1) power supply is still OFF, but can not leak to the NVCC (* 1) power supply terminal (* 2)?
-Step1 : VDD_SNVS_IN (+3.3V)
-Step2 : VDD_HIGH_IN (+3.3V)
-Step3 : VDD_SOC_IN (+1.35V)
-Step4 : NVCC_DRAM (+1.35V)
-Step5 : NVCC(*1) / VDDA_ADC_3P3 / ADC_VREF(+3.3V)
(*1)NVCC : NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD

Thank you.

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mikitakashi
Contributor II

I'm sorry.

The questions duplicated. Please ignore this post.

View solution in original post

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Yuri
NXP Employee
NXP Employee

Hello,

 

 

  The recommended power up sequence of i.MX 6ULL is as following:

 

VDD_SNVS_IN -> VDD_HIGH_IN -> VDD_SOC_IN and all the rest suppliers.

 

  So, You are right, there is no sequence order for NVCC_xxx and VDDA_ADC_3P3, ADC_VREFH.

Your sequence is acceptable. Also, note, the POR_B input must be immediately asserted at power-up

and remain asserted until after the last power rail reaches its working voltage.

 

Have a great day,

Yuri

 

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anton_milochkin
Contributor I

Hello Yuri,

I have a question about i.MX6ULL power supply generally, power-up and power-down sequences.
We have very simplified processor power supply sub-system (without PMIC) and it works. But I want to double check the solution we use.
VDD_SNVS_IN, VDD_HIGH_IN and NVCC_x (excepting NVCC_NAND) are tied together and connected to 3.3V bus. NVCC_NAND is connected to 3.3V>1.8V DC/DC which provides 1.8V automatically with 25ms delay after 3.3V is appeared. VDD_SOC_IN is powered also with DC/DC and it is controlled separately.

In HW guide it is written that if RTC battery is not used, VDD_SNVS_IN and VDD_HIGH_IN could be tied together. Also on evboard schematic VDD_HIGH_IN and NVCC_x are tied to DCDC_3V3 bus.

So, our power-up sequence is following.
1) POR_B pulled down
2) VDD_SNVS_IN, VDD_HIGH_IN and NVCC_x (excepting NVCC_NAND) are powered with 3.3V simultaneously
3) About 25 ms delay
4) NVCC_NAND is powered with 1.8V
5) Some delay
6) VDD_SOC_IN is powered
7) Pause for internal LDO voltages stabilization
POR_B released

Do you see and restrictions?

Also about power-down sequence.
In our system processor is not used all the time when device is switched on. So, we have some MCU which switches on and off the processor (and its power supplies) when it is needed.
All voltages we have for the processor are produced by DC/DCs with quite large capacitors on outputs. So, when we disable power supplies they drop somehow during seconds. Would it be safety for the processor (when it should be disabled) if we will just pull down processor's POR_B and keep power supply voltages dropping?

Thank you!

 

Best regards

Anton

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mikitakashi
Contributor II

Hi Yuri

Thank you

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mikitakashi
Contributor II

I'm sorry.

The questions duplicated. Please ignore this post.

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mikitakashi
Contributor II

Hi Yuri

Thank you very much.

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