Hi,
I read the data sheet of i.MX6ULL Table 42. Asynchronous Mode Timing Parameters.
It shows data setup/hold time at EDO mode.
When EDO mode, NF16=tDSR=18.28nS and NF17=tDHR=11.83nS fixed value. the condition is
While in the Reference manual, there is a description, "If the GPMICLK period is greater than 6ns (and not greater than
12ns), set the GPMI_CTRL1[HALF_PERIOD]=1; This will cause the DLL reference
period (RP) to be one-half of the GPMICLK period." in 29.4.3.2 NAND Asynchronous EDO Mode Timing.
According to this, GPMICLK is between 166MHz to 83MHz, it should be set GPMI_CTRL1[HALF_PERIOD]=1.
However, data sheet describe like above, when GPMICLK is 100MHz , it is GPMI_CTRL1[HALF_PERIOD]=0.
at EDO mode
Question are:
1. Is it OK to set GPMI_CTRL1[HALF_PERIOD]=0 at 100MHz?
2. When set GPMI_CTRL1[HALF_PERIOD]=1, can we still use the data setup time and hold time constant value in data sheet NF16 and NF17?
Best Regards,
Sugiyama
Solved! Go to Solution.
There is a typo in the Section 29.4.3.2 of the i.MX6ULL Reference Manual document. Please refer to the Section 29.6.7 "GPMI Control Register 1 Description (GPMI_CTRL1n)" of the same document. The description of the HALF_PERIOD field says: "Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation". So, this field sould be set to 1 when the GPMI clock period is greater than 16ns (i.e. when the GPMI clock frequency is lower than 62.5MHz). So, for the GPMI clock frequency of 100MHz (clock period is 10ns), the correct GPMI_CTRL1n[HALF_PERIOD] field value is 0, as shown in the Data Sheet document.
Best Regards,
Artur
Hi, Artur,
Thank you for the explanation.
I understood.
Thanks &Regards,
Sugiyama
There is a typo in the Section 29.4.3.2 of the i.MX6ULL Reference Manual document. Please refer to the Section 29.6.7 "GPMI Control Register 1 Description (GPMI_CTRL1n)" of the same document. The description of the HALF_PERIOD field says: "Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation". So, this field sould be set to 1 when the GPMI clock period is greater than 16ns (i.e. when the GPMI clock frequency is lower than 62.5MHz). So, for the GPMI clock frequency of 100MHz (clock period is 10ns), the correct GPMI_CTRL1n[HALF_PERIOD] field value is 0, as shown in the Data Sheet document.
Best Regards,
Artur