i.MX6ULL DDR3 - 512MB IC in 256MB Design

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i.MX6ULL DDR3 - 512MB IC in 256MB Design

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tkl
Contributor II

Hi,

I have the follwing question:

We have a device on the market in which 256MB DDR3 RAM are used. Given the actual IC price situation, 512MB are cheaper and better available than 256MB ICs. Now I made some prototypes with 512MB chips. Our design is made so that we can use 256MB, 512MB and 1024MB, which means the address lines are all routed to the RAM chip.

Now of all my 30 prototypes I have 1 device which only starts when I configure the CPU for 512MB RAM. If I configure it for 256MB RAM, the device does not start into U-Boot. The 29 other devices start fine even if configured for 256MB RAM.

The only difference between the configurations I am aware of is that 256MB (16Bit) use address lines A0-A13, 512MB use A0-A14. This means A14 is NC in an 256MB chip but is connected in a 512MB chip.

Is it possible that the CPU may not start if address line A14 is not configured for usage but on the connected RAM A14 is not NC? This seems to be the only explanation for what I am seeing. That would mean that it is not possible to use 512MB RAMs in our 256MB devices and only make use of half the memory.

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tkl
Contributor II

Hi,

I found the problem. the tRFC timing does not fit. So it is not a good idea to use a 512MB chip with 256MB timings.

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Yuri
NXP Employee
NXP Employee
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