i.MX6ULL: Access EPIT1 via serial download protocol (SDP)

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i.MX6ULL: Access EPIT1 via serial download protocol (SDP)

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285 Views
ceggers
Contributor IV

According to IMX6ULLRM.pdf, Table 8-31. "Valid DCD address ranges", beside IOMUXC, CCM and DDR, also EPIT1 can be accessed from the DCD. As the DCD command set has no "sleep" command, I use EPIT1 together with the DCD's "Check data command" for creating a "sleep". This seems to work fine when booting from (NAND) flash.

For production/recovery we use the internal bootloader for serial download via USB. In this case the DCD is processed by the USB download program on the PC and translated into Serial Download Protocol (SDP) commands. In this scenario, I cannot access the EPIT1 timer.

After enabling all peripheral clock gates, writing to EPIT1_CR/EPIT1_LR fails (I read back all values and compare the result).

My DCD (I use the barebox bootloader with imx-usb-loader):

/* enable all periperhal clock gates */
wm 32 0x020c4068 0xffffffff
wm 32 0x020c406c 0xffffffff
wm 32 0x020c4070 0xffffffff
wm 32 0x020c4074 0xffffffff
wm 32 0x020c4078 0xffffffff
wm 32 0x020c407c 0xffffffff
wm 32 0x020c4080 0xffffffff

/*
* setup epit (must be done separate before enabling)
* - CLKsrc=peripheral clock (IPG_CLK_ROOT=66 MHz)
* - DBGEN = enabled
* - IOVW = enabled
* - RLD = Set And Forget
* - ENMOD = Load value
* - EN = disabled
*/
wm 32 0x020D0000 0x0106000A

--> error: when I read back EPIT1_CR, the value 0x01060000 (without 'A') is read.

/* 3. delay (1 step x 64 cycles / 24 MHz + 1 = 3 us) */
/*udelay(3); 3 us * 66 MHz = 198 (0xC6) */
wm 32 0x020D0008 0x000000C6

--> error: the value 0x00000000 is read back

So how can I access EPIT1 via SDP?

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1 Solution
221 Views
igorpadykov
NXP TechSupport
NXP TechSupport

from team:

----------

Confirmed the issue, have submit to ROM team

----------

Best regards
igor

View solution in original post

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9 Replies
254 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Christian

 

answer from team below:

-------------------

Test on uboot, the epit register can be configured by DCD.

diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg
index 0c64f8179b..32f535f776 100644
--- a/board/freescale/mx6ul_14x14_evk/imximage.cfg
+++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg
@@ -182,6 +182,10 @@ DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
+
+DATA 4 0x020D0000 0x0106000A
+DATA 4 0x020D0008 0x000000C6
+
#endif

-------------------

Best regards
igor

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251 Views
ceggers
Contributor IV

Hi Igor,

seems that "team" has not completely read my problem description...

  • Writing/busy-waiting on EPIT1 from the DCD is NOT the problem
  • But reading EPIT1 registers via the SDP READ_REGISTER command doesn't work

regards,
Christian

 

247 Views
igorpadykov
NXP TechSupport
NXP TechSupport

answer from team below:

-------------------

What is your SDP READ_REGISTER command?

-------------------

Best regards
igor

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226 Views
ceggers
Contributor IV

@igorpadykov: Can you please ping the sw team? I would like to finish this.

regards,
Christian

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222 Views
igorpadykov
NXP TechSupport
NXP TechSupport

from team:

----------

Confirmed the issue, have submit to ROM team

----------

Best regards
igor

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206 Views
ceggers
Contributor IV

Hi Igor,

Confirmed the issue, have submit to ROM team

can this be added to the errata document(s)?

regards,
Christian

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200 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Christian

 

>can this be added to the errata document(s)?

 

decision what should be added to errata document is made by local marketing office management

after confirmation issue by ROM team.

 

Best regards
igor

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244 Views
ceggers
Contributor IV

What is your SDP READ_REGISTER command?

Best regards,
Christian

 

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270 Views
ceggers
Contributor IV

Update: After some debugging through the ROM code, it looks like the SDP read memory command doesn't perform a 32 bit access on the selected register. Instead it uses 8 and 16 bit access together with shift operations for getting a 32 bit value. These type of accesses are probably not supported by the EPIT.

ROM code:

1FFC|2E08 cmp r6,#0x8   // 8 bit?
1FFE|D01E beq 0x203E
2000|2E10 cmp r6,#0x10  // 16 bit?
2002|D055 beq 0x20B0
2004|2E20 cmp r6,#0x20  // 32 bit?
2006|D11C bne 0x2042    // else
2008|E08D b 0x2126      // goto 32 bit
...
// 32 bit
2126|2D00                cmp     r5,#0x0  // count==0?
2128|D1C5                bne     0x20B6   // continue
...
20B6|2600                movs    r6,#0x0  // i=0
20B8|2D40                cmp     r5,#0x40 // (count>64)?
20BA|D311                bcc     0x20E0   // if (count < 64) goto 0x20E0
...
20E0|42AE                cmp     r6,r5    // (i < count)?
20E2|D3EC                bcc     0x20BE   // if (i < count) goto 0x20BE
...
// splitted access to 32 bit register!!!
20BE|7820                ldrb    r0,[r4]     // byte access!
20C0|55B8                strb    r0,[r7,r6]
20C2|8820                ldrh    r0,[r4]
20C4|1C76                adds    r6,r6,#0x1  // i++
20C6|F3C02007            ubfx    r0,r0,#0x8,#0x8
20CA|55B8                strb    r0,[r7,r6]
20CC|6820                ldr     r0,[r4]
20CE|1C76                adds    r6,r6,#0x1  // i++
20D0|F3C04007            ubfx    r0,r0,#0x10,#0x8
20D4|55B8                strb    r0,[r7,r6]
20D6|CC01                ldm     r4!,{r0}
20D8|1C76                adds    r6,r6,#0x1  // i++
20DA|0E00                lsrs    r0,r0,#0x18
20DC|55B8                strb    r0,[r7,r6]
20DE|1C76                adds    r6,r6,#0x1  // i++
20E0|42AE                cmp     r6,r5       // (i < count)?
20E2|D3EC                bcc     0x20BE      // next word

 

Result:

The SDP read command seems to ignore the provided access width. For some peripherals this may work, but for others not. For me this looks like an errata!

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