i.MX6UL DDR3 Design

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i.MX6UL DDR3 Design

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ricardoferreira
Contributor II

Hi,

In the i.MX 6UltraLite Evaluation Kit design, the DDR3 the Address, command and control group are not routed in the same plane. I though these signals needed to be in the same plane. The aproach made in the evaluation board make the routing much easier but is it safe?
Is there any special rule I should follow to route some of these signals in different layers?

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woutersintecs
Contributor II

In general, keep things for the Address/Command/Control bus even, meaning the same length, same reference plane and the same amount of vias.

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igorpadykov
NXP Employee
NXP Employee

Hi Ricardo

this is common approach, described for example in micron app note

https://www.micron.com/~/media/documents/products/technical-note/dram/tn4614.pdf

allowing minimize crosstalk noise. More layout rules can be found in

i.MX6 System Development User’s Guide (rev.1, 6/2013)

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards

igor

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