[i.MX6UL] ADC2

[ceggers]

According to IMX6ULRM.pdf, page 407, both ADCs on MCIMX6G2 should have a similar/same register layout. After investigating ADC2 on MCIMX6G2 it looks like ADC2 has a completely different register layout compared to ADC1.

ADC2 on MCIMX6G2 looks identical to ADC2 on MCIMX6Y2.

Can anybody confirm this?

[art]

Yes, you are right in that the ADC2 module of both i.MX6UL and i.MX6ULL processors has different register layout and different behaviour than ADC1. The reason is that, in addition to ADC1 functionality, ADC2 supports the resistive Touch Screen Controller module. So, for ADC2 description and operation, please refer to the i.MX6ULL Reference Manual document.

Best Regards,
Artur

[ceggers]

Thank you for clarifying this. I would be delighted if this could be fixed in the reference manual (and a new revision of the reference manual would be released more often than a new silicon...)

[joanxie]

what specific difference do you find? could you give me more detailed information? let me double check it.

[ceggers]

At first I tried to do some manuals conversion (write to HC0, wait for HS::COCO, read from R0) with a JTAG debugger. This worked fine for ADC1, but not for ADC2. Also the reset values for ADC_2 differ from ADC_1.

Test with ADC_2 register layout from IMX6ULRM.pdf

ADC1:

- Write 0x00000000 to HC0 (0x0219_8000)
- Debugger shows change in HS (0x0219_8008)

- Can read result from R0 (0x0219_800C)

ADC2:

- Write 0x00000000 to HC0 (0x0219_C000)

- Debugger shows change in CFG (0x0219_C014) and GC (0x0219_C018)

- No change in HS (0x0219_C008).

Reset values:

Test with ADC_2 register layout from IMX6ULLRM.pdf

ADC2:

- Write 0x00000000 to HC0 (0x0219_C000)

- Debugger shows change in HS (0x0219_C014)

- Can read result from R0 (0x0219_C018)

Reset values: