i.MX6SoloX Stop mode

[davidjaouen]

Hello,

I'm trying to set the i.MX6SX into Stop mode.

I use a i.MX6SoloX Sabre SD board. The software boots U-Boot on QSPI2.

I use U-Boot to load software in OCRAM and start it (no Linux OS loaded):

=> tftpboot 0x00900000 192.168.64.144:A9_i.MX6_PowerMgmt.bin; dcache off; go 0x00900000

Here is the piece of code (executing on Cortex-A9):

int main(int argc, char **argv)

{

    CCM_MemMapPtr ccm = (CCM_MemMapPtr)CCM_BASE_ADDR;

    PGC_MemMapPtr pgc = (PGC_MemMapPtr)GPC_BASE_ADDR;

    ccm->CLPCR    = (ccm->CLPCR & ~CCM_CLPCR_LPM_MASK) | 0x02;  // Set the LPM bits to Stop mode 

    ccm->CCR      = ccm->CCR      | CCM_CCR_RBC_EN_MASK;        // Set RBC_EN bit in CCM_CCR register

    pgc->CPU_CTRL = pgc->CPU_CTRL | PGC_CPU_CTRL_PCR_MASK;      // Set PCR bit in PGC_CPU_CTRL register

    __asm volatile ("wfi");                                     // Should enter Stop mode

    for(;;);

    return 0;

}

The problem is that when executing the WFI instruction, the i.MX6SX is reset. U-Boot shows the reset was caused by a watchdog time-out.

When RBC_EN bit is not set, the Cortex-A9 enters in wait for interrupt state but the whole chip does not enter in Stop mode.

So, what am I missing to enter the chip in Stop mode?

Regards,

David

PS1: I know there is other operations to do to wake up properly from Stop mode, but this is the next step. For now, I'm just trying to enter into Stop mode.

PS2: I determined the chip mode by tracking the current consumption on VDD_ARM_IN and VDD_SOC_IN supply lines.

[igorpadykov]

Hi David

for wdog one can set its low power modes using bit

WDZST (regiister WDOGx_WCR), note WDZST, WDBG and WDW are

write-once only bits.

Best regards

igor

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[davidjaouen]

Hi Igor,

No watchdogs was enabled. But I found that it is necessary to wait for at least 2 cycles of CKIL clock before executing

WFI instruction. So, the system does not reset anymore but I'm still unable to enter in wait or stop mode.

I programmed the CGR registers in the CCM so modules clocks be disabled when entering wait or stop mode. But when the

Cortex-A9 executes the WFI instruction, no clocks are disabled .

Any idea?

Best regards,

David

[igorpadykov]

HI David

one can look at suspend sequence imx6_suspend() in suspend-imx6.S,

it can be found using sect.22.1.2 Source Code Structure attached Linux

Manual. One can printf (or check with jtag) its registers and compare with

own application.

Best regards

igor

[davidjaouen]

Thanks Igor.

I had a look to the imx6_suspend() function and finally succeeded in putting the i.MX6SX in

deep sleep mode.

It seems there is a bug in the i.MX6SX reference manual, in the description of the CCM CLPCR

register (section 19.6.18). The bypass_mmdc_lpm_hs bit seems to be located at bit 19, not 21.

Can you confirm?

Regards,

David