i.MX6Solo Ethernet TX Clock problem

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

i.MX6Solo Ethernet TX Clock problem

Jump to solution
705 Views
donghyunkim
Contributor III

Hi.

I'm using i.mx6solo custom board and yocto 4.14.98.

To use Ethernet, the dts are set up as below.

&fec {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet>;
    phy-mode = "rgmii";
    phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
    fsl,magic-packet;
    status = "okay";
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        dp83867: ethernet-phy@0 {
            compatible = "ethernet-phy-id2000.a231";
            ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
            ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
            ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
            reg = <0>;
        };
    };
};

pinctrl_enet: enetgrp {
    fsl,pins = <
        MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
        MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
        MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
        MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
        MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
        MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
        MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
        MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
        MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
        MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
        MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
        MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
        MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
    >;
};

pinctrl_enet_irq: enetirqgrp {
    fsl,pins = <
        MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
    >;
};

 

Connecting Ethernet to the board makes it a linkup.

[ 2599.634982] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 2603.680566] fec 2188000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[ 2603.680616] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

 

However,

If 100M is connected, the TX_CLK outputs to 5MHz. (25MHz is correct)
If 1G is connected, the TX CLK outputs to 25MHz. (125MHz is correct)
RX_CLK outputs 25MHz when connecting 100M, and 125MHz when connecting 1G.

Question.

I understand that TX_CLK is generated from MX6QDL_PAD_GPIO_16_ENET_REF_CLK. 

Which part should I modify to get TX_CLK output normally?

 

Thanks all.

0 Kudos
1 Solution
2 Replies
695 Views
donghyunkim
Contributor III

hi, igorpadykov.

The information you gave me helped me understand a lot.

Thanks.

0 Kudos