i.MX6SX MMDC support

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i.MX6SX MMDC support

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ko-hey
Senior Contributor II

Hi all

I'm confused about i.MX6SX's MMDC support.

Because there're some different description in RM.

So please teach me following questions.

1. How many chip select can we use when select a DDR3 device ?

There are following description in Table 40-1 of RM.

So I guess we can use only one chip select when user select DDR3.

Is it correct ?

"Two chip selects (one chip select for DDR3/LVDDR3, two chip selects for LPDDR2)"

2. How much does the maximum density of i.MX6SX ?

There're two descriotions about address space in RM.

P278 「DDR interface : Up to 2 Gbyte address space and configurable address space per CS.」、

P2538「DDR interface : Up to 4 Gbytes of address space with configurable partitioning between CS0 and CS1」

From above descriptions, if we can use two CS, i.MX6SX can support 4GB.

However, i.MX6SX can use only one CS when user selects DDR3.

As a result, i.MX6SX can support only 2GB when selects DDR3.

Is it correct ?

3. Which is correct description about density ?

P278 「DDR interface : Density of 256 Mbytes-8 Gbytes」

P2538 「DDR interface : Density per DDR device of 256 Mbits–8 Gbits with ~」

Which description is correct ?

4. What is correct connection between i.MX6SX and DDR3 ?

There's a figure that is connection between i.MX 6SX and DDR3 in IMX6SXHDG.

The data bus of i.MX6SX side is DRAM_D[15:0], but data bus of DDR3 side is DQ[31:0].

How can I interpret it ?

Please teach me your assumption.

Ko-hey

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1 Solution
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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  The i.MX 6SoloX supports single Chip Select DDR3 memory with CS0_B, ODT0, and SDCKE0 ;

up to 2GBytes is reserved in system memory.

  For connection scheme, please use the reference design.
SABRE Board Reference Design|NXP

Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  The i.MX 6SoloX supports single Chip Select DDR3 memory with CS0_B, ODT0, and SDCKE0 ;

up to 2GBytes is reserved in system memory.

  For connection scheme, please use the reference design.
SABRE Board Reference Design|NXP

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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ko-hey
Senior Contributor II

Hi Yuri

Thank you for your response.

Where can I find the description ?

i.MX6SX has 32bit address bus so it can support 4GB.

Why i.MX6SX can only support 2GB ?

Do you have any reason why is restricted ?

Ko-hey

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Yuri
NXP TechSupport
NXP TechSupport

Hi,

please use Table 2-1 (System memory map) of the i.MX6 SX RM.

Regards,

Yuri.

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ko-hey
Senior Contributor II

Hi Yuri

I understand that it has no special reason and i.MX6SX can support only 2GB.

Ko-hey