Hello Freescale Community,
I thought I had successfully compiled and ported the uboot and kernel along with file system onto an SD card (2 partitions 1 for the bootloader and kernel the other for the fs).
However upon trying to test on the i.MX6SL EVK board through SD2 I found that the board does not boot.
Swapping out to the original MX6LEVK LCD ANDROID r12.10.02 SD card resulted in a non-response as well.
My workstation and Terra Term both still detected connectivity to the board, but there was no boot splash.
Wanting to test the functionality of the board I attempted to run the DDR Stress Tester 1.03 provided by Freescale and found that to still function.
As shown below:
******************************
DDR Stress Test (1.0.3) for MX6SL
Build: Jun 25 2014, 12:09:06
Freescale Semiconductor, Inc.
******************************
=======DDR configuration==========
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 8
Row size: 14, col size: 10
Both chip select CSD0 and CSD1 are used
Density per chip select: 512MB
==================================
What ARM core speed would you like to run?
Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz
ARM set to 1GHz
Please select the DDR density per CHANNEL (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6
for 32MB
Note, if there are two chip selects per channel, then input the combined densit
y of
both chip selects per channel
DDR density selected (MB): 1024
Calibration will run at DDR frequency 400MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
DDR Freq: 396 MHz
Would you like to run the read/write calibration? (y/n)
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 0001:byte 0 fail.
result 0011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x1111
....
MMDC0 MPRDDLCTL = 0x40404046
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x1111
....
MMDC0 MPWRDLCTL = 0x3630342E
MMDC registers updated from calibration
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404046
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3630342E
The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same valu
e
Would you like to run the DDR Stress Test (y/n)?
Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
396
The freq you entered was: 396
Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
396
The freq you entered was: 396
Beginning stress test
loop: 1
DDR Freq: 396 MHz
t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test
=====================================================
Is there anything obvious as to why the board seems to be not booting from SD2?
Any feedback would be appreciated.
Tae Kim
