i.MX6SDL eCSPI behavior in slave mode.

[satoshishimoda]

Hi community,

We want to confirm about i.MX6SDL eCSPI behavior.

Please see our questions as below.

[Q1]

Please see chapter 21.7.5 in IMX6SDLRM (Rev.1).

In slave mode when SS_CTL=0, we guess i.MX6SDL eCSPI does NOT input/output data if SS signal is negated.

Is this correct?

Or SS signal is ignored and i.MX6SDL inputs/outputs with only SPI clock even if SS signal is negated?

[Q2]

In slave mode when SS_CTL=1, we understand RXFIFO is advanced whenever a SS signal edge that shows burst complete, and RXFIFO is NOT advanced whenever a SS signal edge that shows burst start.

Is this correct?

And then, how about TXFIFO?

Is TXFIFO advanced at the same time as RXFIFO? or is TXFIFO not advanced by SS signal edge?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

1.>In slave mode when SS_CTL=0, we guess i.MX6SDL eCSPI does NOT input/output data if SS signal is negated.

Correct.

2.>In slave mode when SS_CTL=1, we understand RXFIFO is advanced whenever a SS signal

>edge that shows burst complete, and RXFIFO is NOT advanced whenever a SS signal edge that shows burst start.

Correct.

Also TXFIFO advanced at the same time as RXFIFO.

Best regards

igor

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[satoshishimoda]

Hi Igor,

Thank you for your prompt reply.

According to your reply, I understood a SS signal edge of "burst start" does NOT affect to any shift registers and FIFOs advancing, right?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

you were correct that

RXFIFO is advanced whenever a SS signal edge that shows burst complete,

and RXFIFO is NOT advanced whenever a SS signal edge that shows burst start.

Best regards

igor

[satoshishimoda]

Hi Igor,

I have one more question.

Are TXFIFO and RXFIFO advanced by SS burst complete edge when "SS_CTL=0" in slave mode also?

Or nothing happens when SS_CTL=0?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

this case is decribed in sect.21.7.4 Config Register (ECSPIx_CONFIGREG) IMX6DQRM

SS_CT = 0 In slave mode - an SPI burst is completed when the number

of bits received in the shift register is equal to (BURST LENGTH + 1).

Best regards

igor

[satoshishimoda]

Dear Igor,

Thank you for your reply, but your reply was not the one we expected.

My question is "Is FIFO advancing timing same as SS_CLT=1 even though SS_CLT=0?".

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

FIFO SS_CLT=1 advancing timing is different from SS_CLT=0

Best regards

igor

[satoshishimoda]

Hi Igor,

> FIFO SS_CLT=1 advancing timing same is different from SS_CLT=0

Excuse me, same? different? which is correct?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

reason may be i.MX53 CSPI errata ENGcm10189 ,

which also affects i.MX6 series (errata updates planned

for the next revs).

Best regards

igor

[satoshishimoda]

Please note that my question is the advancing timing when "SS_CTL=0".

ENGcm10189 does not happen when SS_CTL=0, doesn't it?

Best Regards,

Satoshi Shimoda

[igorpadykov]

i.MX53 CSPI errata ENGcm10189 gives clear answer on your question

on thread above:

Q:

"My question is "Is FIFO advancing timing same as SS_CLT=1 even though SS_CLT=0?"."

A: from ENGcm10189:

There is no workaround except for not using the SSB_CTRL[x] = 1 option in the Slave mode.

>My question is "Is FIFO advancing timing same as SS_CLT=1 even though SS_CLT=0?".

No.

Supported only option SS_CLT=0—SPI burst completed when (BURST_LENGTH + 1) bits are received

~igor

[satoshishimoda]

> There is no workaround except for not using the SSB_CTRL[x] = 1 option in the Slave mode.

> Supported only option SS_CLT=0—SPI burst completed when (BURST_LENGTH + 1) bits are received

OK, I understood SS_CTL=1 is not supported since ENGcm10189.

So please tell me the timing when FIFO is advanced with SS_CTL=0 in the slave mode?

By SS negation edge? or it is depends on application?

Best Regards,

Satoshi Shimoda

[igorpadykov]

From ENGcm10189 erratum:

Supported only option SS_CLT=0—SPI burst completed when (BURST_LENGTH + 1) bits are received

Slave mode with unspecified burst length cannot be supported due to this issue. The burst length

should always be specified with the BURST_LENGTH parameter and the SSB_CTRL[x] should

be set to zero.

>timing when FIFO is advanced with SS_CTL=0 in the slave mode

This is defined by event when all (BURST_LENGTH + 1) bits are received (burst completed).

Best regards

igor

[satoshishimoda]

Hi Igor,

> This is defined by event when all (BURST_LENGTH + 1) bits are received (burst completed).

I understood TXDATA is loaded to shift register from FIFO for each word, and RXDATA is fetched to FIFO from shift register for each word.

Then, I guess the first FIFO is used for loading/fetching data and TXDATA/RXDATA is advanced to forward FIFO when the interval of each word transfer.

But according to you reply, TXDATA/RXDATA is not advanced until burst complete event.

In this case, 1st FIFO is used for 1st word transfer, and 2nd FIFO is used for 2nd word transfer, right?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

I think I already answered original question Q1,Q2:

SS signal is not used due to ENGcm10189 erratum.

For new questions please create new Community thread.

Thanks!

~igor

[igorpadykov]

Please note that may answer was on your question below:

Question:

> FIFO SS_CLT=1 advancing timing same is different from SS_CLT=0

>Excuse me, same? different? which is correct?

Answer: reason may be i.MX53 CSPI errata ENGcm10189

Best regards

igor