i.MX6Quad AUDMUX Unused Timing Signal Lines

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i.MX6Quad AUDMUX Unused Timing Signal Lines

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paul_katarzis
Contributor III

I am working with a system that uses an i.MX6Quad and two external audio codecs that need to act as I2S slaves. Both audio codecs share the same bit clock line and the same frame synchronization line. Each audio codec has its own TXD and RXD lines. The audio codecs do not support network mode and therefore must send and receive their data to separate SSI modules. The first audio codec data lines are connected to port 3 of AUDMUX and the second audio codec data lines are connected to port 4 of AUDMUX. The common bit clock line and frame synchronization lines are connected to port 3 of AUDMUX.

I would like SSI 1 to send and receive data from the audio codec on port 3 and would like SSI 2 to send and receive data from the audio codec on port 4. In this case, SSI 1 would be an I2S master and supply the bit clock and frame synchronization signals to both audio codecs over port 3. SSI 2 would then have to be an I2S slave and also receive the bit clock and frame synchronization signals from SSI 1 over port 1.

With this configuration, port 4 does not need to produce or consume any timing signals. Port 4 only needs to use its TXD and RXD lines. Is it possible to configure AUDMUX to do this? The only options I see for timing signal lines are to set them as either inputs or outputs. What if these lines act as neither inputs or outputs?

1 Solution
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igorpadykov
NXP Employee
NXP Employee

Hi Paul

I believe such configuration is possible using AUDMUX_PTCR4 settings

described insect.16.6.7 Port Timing Control Register 4 (AUDMUX_PTCR4),

general AUDMUX structure is described in Figure 16-1. AUDMUX Block Diagram
i.MX6DQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

May be useful to check Table 81. AUDMUX Port Allocation i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

AN2628 Programming Audio Applications
http://www.nxp.com/docs/en/application-note/AN2628.pdf

Best regards
igor
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5 Replies
809 Views
igorpadykov
NXP Employee
NXP Employee

Hi Paul

I believe such configuration is possible using AUDMUX_PTCR4 settings

described insect.16.6.7 Port Timing Control Register 4 (AUDMUX_PTCR4),

general AUDMUX structure is described in Figure 16-1. AUDMUX Block Diagram
i.MX6DQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

May be useful to check Table 81. AUDMUX Port Allocation i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

AN2628 Programming Audio Applications
http://www.nxp.com/docs/en/application-note/AN2628.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

808 Views
paul_katarzis
Contributor III

I looked at AN2628, but all of the examples show the timing lines being used. If I were to set TFS_DIR, TCLK_DIR, RFS_DIR, and RCLKDIR as inputs, but provide no actual timing signals on the timing lines, will data flow through the data transmit and receive lines without any issues?

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808 Views
igorpadykov
NXP Employee
NXP Employee

no, without clocks SSI will not operate properly.

Best regards
igor

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808 Views
paul_katarzis
Contributor III

I understand that SSI will not work properly, but will AUDMUX ports still work without any issue?

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igorpadykov
NXP Employee
NXP Employee

yes