i.MX6Q SabreSD CPU Core 2 & 3 stopped working

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i.MX6Q SabreSD CPU Core 2 & 3 stopped working

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Tarek
Senior Contributor I

Hi All,

I was running some PCIe tests on SabreSD board. The 4 CPU cores and the PCI worked fine. When I changed the PCIe card the PCI link stopped working. When I started debugging the problem I found that Core 2 and Core 3 are not working! only core0 and core1 are running:

root@imx6qsabresd:~# cat /proc/cpuinfo

processor       : 0

model name      : ARMv7 Processor rev 10 (v7l)

BogoMIPS        : 3.00

Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32

CPU implementer : 0x41

CPU architecture: 7

CPU variant     : 0x2

CPU part        : 0xc09

CPU revision    : 10

processor       : 1

model name      : ARMv7 Processor rev 10 (v7l)

BogoMIPS        : 3.00

Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32

CPU implementer : 0x41

CPU architecture: 7

CPU variant     : 0x2

CPU part        : 0xc09

CPU revision    : 10

Hardware        : Freescale i.MX6 Quad/DualLite (Device Tree)

Revision        : 0000

Serial          : 0000000000000000

The output of bare-metal SDK also shows that only Core0 and Core1 are running:

  Select test to run:

mc

Running the GIC Multicore Test

Starting and sending SGIs to secondary CPUs for "hello world"

secondary main cpu: 1

Is there any chip registers that I can check to get more information about the cores and enable the 2 disabled cores?

I still can run Linux, network, ssh , uart console, ...etc Is it possible that the i.MX6 Chip was damaged?

Thanks,

Tarek

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Tarek
Senior Contributor I

Hi Yuri,

I think I found the problem. I have accidentally written to Core2&3 power gating OTP register.

root@imx6qsabresd:/unit_tests# ./memtool -32 0x021BC4D0 1

E

Reading 0x1 count starting at address 0x021BC4D0

0x021BC4D0:  80000000

Now the 2 cores gone forever ......:smileysad:

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Yuri
NXP Employee
NXP Employee

Hello,

  Please check if VDD_ARM23_IN is proper.

Also, You may use the example in attachment of the following thread

to check multi-core operations.

Integrating Processor Expert for i.MX and ARM GCC with Eclipse


Have a great day,
Yuri

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542 Views
Tarek
Senior Contributor I

Hi Yuri,

I think I found the problem. I have accidentally written to Core2&3 power gating OTP register.

root@imx6qsabresd:/unit_tests# ./memtool -32 0x021BC4D0 1

E

Reading 0x1 count starting at address 0x021BC4D0

0x021BC4D0:  80000000

Now the 2 cores gone forever ......:smileysad:

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541 Views
Yuri
NXP Employee
NXP Employee

:-)

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