i.MX6Q SABRE SD - How to use FEC phy gpio IRQ

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i.MX6Q SABRE SD - How to use FEC phy gpio IRQ

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petertseng
Contributor III

Hello,


We are i.MX6Q Sabre SD board using Qualcomm Atheros AR8033 phy chip.

We found some code references AR8031 registers board-mx6q_sabresd.c board initialization file.

I need to interrupt pin GPIO_1_6 change GPIO_1_26

#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO

#define MX6_ENET_IRQ IMX_GPIO_NR(1, 26) //IMX_GPIO_NR(1, 6)

#define IOMUX_OBSRV_MUX1_OFFSET 0x3c

#define OBSRV_MUX1_MASK 0x3f

#define OBSRV_MUX1_ENET_IRQ 0x9

#endif

static struct fec_platform_data fec_data __initdata = {

  .init = mx6q_sabresd_fec_phy_init,

  .phy = PHY_INTERFACE_MODE_RGMII,

#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO

  .gpio_irq = MX6_ENET_IRQ,

#endif

};

static void __init mx6_sabresd_board_init(void)

{

.........

  imx6_init_fec(fec_data);

#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO

  /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */

  mxc_iomux_set_specialbits_register(IOMUX_OBSRV_MUX1_OFFSET,

  OBSRV_MUX1_ENET_IRQ, OBSRV_MUX1_MASK);

#endif

......

}

Thank you for anyone that will give us some hints.

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9 Replies

126 Views
AnsonHuang
NXP Employee
NXP Employee

Hi, Peter

     To enable FEC GPIO irq, you can enable this CONFIG_MX6_ENET_IRQ_TO_GPIO in menuconfig->system type->freescale mxc implementations->route ENET interrupt to GPIO.

     If you select this config, this pin MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 will be configured to issue an interrupt to GPIO1_6.

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petertseng
Contributor III

Hi Yongcai

     The AR8033 irq currently used GPIO1_26 on my board.

     How to change ethernet's irq using GPIO1_26.

Best regards,

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126 Views
AnsonHuang
NXP Employee
NXP Employee

Hi, Peter

     I think this is totally two different things. The enet's irq means internal ENET MAC's irq, it has a function to route internal irq out to GPIO_1_6, it is a debug function and can NOT use other pins;

     Your question is about external AR8033 pht's irq, it is connected to GPIO_1_26, right? Then you can just set this GPIO_1_26 to input mode, then receive the irq signal from AR8033, it is a normal GPIO irq, not ENET internal MAC's irq.

     Am I correct about your question?

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petertseng
Contributor III

Hi Yongcai


     So, you mean only use GPIO_1_6 for ENET MAC's IRQ?


Best regards,

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126 Views
AnsonHuang
NXP Employee
NXP Employee

GPIO_1_6 can be used as ENET MAC’s irq, but this is not a default configuration, but only a workaround to fix a ENET errata in order to improve performance when low power mode is enabled.

Normally, ENET has its own irq number.

And I think for you case, you want to know external PHY’s irq, it is connected to another GPIO_1_29, right? So this is a different issue.

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

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126 Views
petertseng
Contributor III

Hi Yongcai

    

     Currently board AR8033 PHY is directly connected to ENET RGMII interface, and PHY's interrupt is connected to the GPIO_1_26, Wake-on-LAN interrupt is connected to GPIO_1_25.

    

     I have tried to do is not use the external interrupt,  the kernel crashed randomly after initializing the FEC.

     https://community.freescale.com/thread/308350

Best regards,

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126 Views
AnsonHuang
NXP Employee
NXP Employee

You are using TO1.0, right? This is an known issue for TO1.0. Can you tell me the TO version you used? You can get it in the start of uboot log. Or you can read addr 0x48 directly to get ROM version.

126 Views
petertseng
Contributor III

Hi Yongcai.

It is TO1.1, and use Android JB4.2.2 version.

Try "enable_wait_mode = off" option, does not have KERNEL crash.

The new i.MX6 chips do not need to use "enable_wait_mode = off" option?


Best regards,

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AnsonHuang
NXP Employee
NXP Employee

Yes.

For i.MX6Q TO1.2, i.MX6DL TO1.1(in a word, latest TOs), there is no such crash issue, this is a known issue on old TOs.

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058