Background: I'm revisiting an old project that uses the i.MX6Q POP with MT42L128M64D2LL LPDDR2. The board is strapped for single channel mode to allow for smaller DRAM chips in production and fuses are set to enable dual-channel 4K interleaving at the end of the provisioning process if needed. This worked fine years ago with a pin-compatible DRAM chip from Micron but a recent batch of factory-fresh boards fails in SD uBoot SPL as soon as the DRAM is accessed.
My questions relate mostly to the i.MX 6/7 DDR Stress Test Tool v3.0 and its behavior. To rule out counterfeit DRAM, I'm attempting to use the new stress test tool over USB. I can connect to the board and load the binary fine using an .inc file generated by MX6Q_MMDC_LPDDR2_register_programming_aid_v1.5 (the DRAM chip used matches the one on NXP's validation board). The config is read correctly and I can start a calibration at 300-400MHz. Unfortunately, the calibration fails completely which leads me to a few questions:
- Has v3.0 of the Stress Test Tool been validated against the i.MX6Q POP variant used on NXP's validation board?
- Is it normal for the test tool to go directly to read calibration? This is the behavior I'm seeing while older logs posted on the community show write leveling and DQS calibration happening before this which I found odd.
- Has anyone seen counterfeit POP packaged DRAM under the current market conditions? These are quite old, so I wouldn't be surprised if my client's broker came across bad chips.
See the attached log for further details.
