i.MX6Q PCI Express Endpoint Bass Address Boundary

[masamiyasui]

We would like to use i.MX 6Q as the PCI Express endpoint.
Please tell us about the boundary of the address of the local memory assigned to BAR.

48.12.45 iATU Region Lower Base Address Register
(PCIE_PL_iATURLBA)
 
Is not this register setting 64 KB boundary?

It seems that it will not work unless we set the same boundary as the BAR capacity (BAR_MASK).

Is this specification of iATU?

Note: We are using iATU in BAR Mode.

48.12.44 iATU Region Control 2 Register (PCIE_PL_iATURC 2)
Bit 30 Match_Mode = 1 (BAR Mode)

[Yuri]

Hello,

   According to Table 48-20 (Configuration Parameters Relevant to Address Translation)

of i.MX6 D/Q RM (Rev. 4, 09/2017):

CX_ATU_MIN_REGION_SIZE (Minimum Size of Address Translation Region) is 64 kB.

  Note, from i.MX6 D/Q RM (section 48.10.5 [BAR 0 Mask Register (PCIE_EP_MASK0)]):

The core requires each memory BAR to claim at least 4 KB. The core requires each I/O

BAR to claim at least 256 bytes.

Have a great day,
Yuri

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