i.MX6Q LVDS Wrong clock issue

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX6Q LVDS Wrong clock issue

Jump to solution
8,508 Views
ettorechimenti
Contributor II

Hi all,

I have a custom iMX6q derived from SABRE and I wanted to use a 7 inches 800x480 WVGA monitor attached to the LVDS channel 0.

The monitor works with an operating clock freq at 33.26 MHz, but it works well even with 38MHz (tested).

I'm using kernel 3.14.28_ga, I've modified the original SABRE DTS specifing:

        mxcfb1: fb@0 {

            compatible = "fsl,mxc_sdc_fb";

            disp_dev = "ldb";

            interface_pix_fmt = "RGB666";

            mode_str ="LDB-WVGA";

            default_bpp = <32>;

            int_clk = <0>;

            late_init = <0>;

            status = "okay";

        };

&ldb {

    status = "okay";

    primary;

   

    lvds-channel@0 {

        reg = <0>;

        fsl,data-mapping = "spwg";

        fsl,data-width = <18>;

        status = "okay";

        crtc = "ipu1-di0";

        display-timings {

            native-mode = <&timing1>;

            timing1: 800x480 {

                clock-frequency = <38000000>;

                hactive = <800>;

                vactive = <480>;

                hback-porch = <56>;

                hfront-porch = <50>;

                vback-porch = <23>;

                vfront-porch = <20>;

                hsync-len = <150>;

                vsync-len = <2>;

            };

        };

    };

};

From dmesg output:

mxc_sdc_fb fb.18: registered mxc display driver ldb

Console: switching to colour frame buffer device 100x30

The LVDS manages to light up, but remains blank.

Testing with an oscilloscope it seems the clock output is giving 76MHz instead!

How can I set the right clock frequency?

Any ideas?

- ec

Labels (4)
Tags (4)
0 Kudos
1 Solution
741 Views
ettorechimenti
Contributor II

Thanks everyone for answering,

Unfortunately, the solutions didn't work for me.

I've done some research and found a workaround (and, I think, the problem).

I found that the u-boot sets the various parent clocks before boot, but the kernel don't overwrite this setting (the specification in clk-imx6q.c doesn't apply).

Specifically, testing with devmem2 after boot :

CCM_CS2CDR (0x20C_402C) -> 0x007206C1  //MMDC_CH1 enabled on LDB_DI0_CLK_SEL)

After recompiling the uboot, setting manually the parent to PLL5_VIDEO, the issue disappear, and the kernel manages to control the PLL to the correct frequency.

I've added in the uboot platform file (board/freescale/mx6sabresd/mx6sabresd.c

  /* Turn on LDB0,IPU DI0 clocks */

  reg = __raw_readl(&mxc_ccm->CCGR3);

  reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;

  writel(reg, &mxc_ccm->CCGR3);

  /* set LDB0 clk select to 000 (pll5) */

  reg = readl(&mxc_ccm->cs2cdr);

  reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);

  reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->cs2cdr);

       

  /* LDB clock div by 7 */

  reg = readl(&mxc_ccm->cscmr2);

  reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;

  writel(reg, &mxc_ccm->cscmr2);

  /* derive ipu1_di0_clk_root clock from ldb_di0_clk */

  reg = readl(&mxc_ccm->chsccdr);

  reg |= (CHSCCDR_CLK_SEL_LDB_DI0

  << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->chsccdr);

After boot:

CCM_CS2CDR (0x20C_402C) -> 0x007200C1  //PLL5_CLK enabled on LDB_DI0_CLK_SEL

Maybe the kernel fails to write the registers in the initialization process?

Thanks again, - ec

View solution in original post

0 Kudos
8 Replies
741 Views
Ansari
Contributor IV

Hi,

I believe, the parent clock is not mapped.  You need to set the parent for LDB_DI0_SEL.

In IPU clock selection section, add the below changes in "~/linux-imx/arch/arm/mach-imx/clk-imx6q.c" file.

    /* ipu clock initialization */
    imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);

Regards,

Ansari

741 Views
csotoalonso
Contributor III

That worked for  me, thanks!

0 Kudos
742 Views
ettorechimenti
Contributor II

Thanks everyone for answering,

Unfortunately, the solutions didn't work for me.

I've done some research and found a workaround (and, I think, the problem).

I found that the u-boot sets the various parent clocks before boot, but the kernel don't overwrite this setting (the specification in clk-imx6q.c doesn't apply).

Specifically, testing with devmem2 after boot :

CCM_CS2CDR (0x20C_402C) -> 0x007206C1  //MMDC_CH1 enabled on LDB_DI0_CLK_SEL)

After recompiling the uboot, setting manually the parent to PLL5_VIDEO, the issue disappear, and the kernel manages to control the PLL to the correct frequency.

I've added in the uboot platform file (board/freescale/mx6sabresd/mx6sabresd.c

  /* Turn on LDB0,IPU DI0 clocks */

  reg = __raw_readl(&mxc_ccm->CCGR3);

  reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;

  writel(reg, &mxc_ccm->CCGR3);

  /* set LDB0 clk select to 000 (pll5) */

  reg = readl(&mxc_ccm->cs2cdr);

  reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);

  reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->cs2cdr);

       

  /* LDB clock div by 7 */

  reg = readl(&mxc_ccm->cscmr2);

  reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;

  writel(reg, &mxc_ccm->cscmr2);

  /* derive ipu1_di0_clk_root clock from ldb_di0_clk */

  reg = readl(&mxc_ccm->chsccdr);

  reg |= (CHSCCDR_CLK_SEL_LDB_DI0

  << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->chsccdr);

After boot:

CCM_CS2CDR (0x20C_402C) -> 0x007200C1  //PLL5_CLK enabled on LDB_DI0_CLK_SEL

Maybe the kernel fails to write the registers in the initialization process?

Thanks again, - ec

View solution in original post

0 Kudos
741 Views
osmarfrisonjun1
Contributor III

Hello

When I apply the changes, the boot stops at "switch to ldo_bypass mode!":

U-Boot 2014.04 (Jul 22 2015 - 09:46:08)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz

CPU:   Temperature 10 C, calibration data: 0x5614cb7d

Reset cause: POR

Board: MX6-SabreSD

I2C:   ready

DRAM:  1 GiB

MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

No panel detected: default to Hannstar-XGA

Display: Hannstar-XGA (1024x768)

In:    serial

Out:   serial

Err:   serial

Found PFUZE100 deviceid=10,revid=10

mmc0 is current device

Net:   FEC [PRIME]

Normal Boot

Hit any key to stop autoboot:  0

mmc0 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

5930352 bytes read in 274 ms (20.6 MiB/s)

Booting from mmc ...

reading imx6q-sabresd.dtb

42259 bytes read in 19 ms (2.1 MiB/s)

Kernel image @ 0x12000000 [ 0x000000 - 0x5a7d70 ]

## Flattened Device Tree blob at 18000000

   Booting using the fdt blob at 0x18000000

   Using Device Tree in place at 18000000, end 1800d512

switch to ldo_bypass mode!

Any Idea?

Thanks.

0 Kudos
741 Views
laszlotimko
Contributor III

Hi,

I think pll5 is not initialized in u-boot, this might be the reason of your freeze. There are two possible workarounds for this issue:

  • Enable pll5 in u-boot. Unfortunately, I haven't found working patch for newer kernel, however you can download a "0002-Support-LVDS-clock-source-from-PLL5.patch" file from this link: https://community.freescale.com/docs/DOC-98109. It is for android u-boot but it would be a good starting point.
  • Completely disable lvds section in u-boot (disable CONFIG_VIDEO_IPUV3) and entrust clock initialization to linux kernel. One great drawback to this method you will no longer get u-boot logo.

Regards

0 Kudos
741 Views
Ansari
Contributor IV

Hi,

Thank you for your input.

In U-boot level, we are not supporting any display(including LVDS) and we are supporting the displays (including LVDS) in kernel level only.

As per your referred community link, the LVDS clock parent settings has to be added during the "setup_display".

But in our case(in our custom board file) "setup_display" function is not there.

Please suggest us.

Regards,

Ansari

0 Kudos
741 Views
ettorechimenti
Contributor II

Hi, Ansari

I used this source file, and "setup_display" is present:

http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx6sabresd/mx6sabresd.c...

Isn't a valid version?

Btw, adding code in uboot actually is a workaround, I would like to set the right PLL in kernel boot process.

There is a bug in 3.14.28_ga?

Cheers, Ettore

0 Kudos
741 Views
alejandrolozan1
NXP Employee
NXP Employee

Hi,

I have not tried that out. But you may try to change or select a different parent clock. And after looking at the code you could try to select the slipt-mode too.

You can try to add  split-mode in the device node.

serial_clk = ldb->spl_mode ? chan.vm.pixelclock * 7 / 2 :

                        chan.vm.pixelclock * 7;

please let me know if that makes a difference.

Best Regards,

Alejandro

0 Kudos