i.MX6Q: Downgrade ARM speed to 400Mhz before ldo bypassed

[norishinozaki]

Hello Champs,

I found this comment in u-boot 2014-04 arch/arm/cpu/armv7/mx6/soc.c

void prep_anatop_bypass(void)

{      

    struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

    arm_orig_podf = readl(&mxc_ccm->cacrr);

    /* 

    * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo

     * bypassed, also downgrade internal vddarm ldo to 0.975V.

     * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)

     * otherwise at 800Mhz(i.mx6dl):

     * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)

     * We need provide enough gap in this case.

Why do we need to downgrade to 400MHz?

BR,

NS.

[norishinozaki]

Igor,

Thanks & BR.

NS

[norishinozaki]

Igor,

>so setting MMPF0100 1.275V with 25mV accuracy setting is not good .

1.275V is actually used in the u-boot code.

Is 1.300V OK? it's the max though.

void ldo_mode_set(int ldo_bypass)

{

    unsigned char value;

    int is_400M;

    u32 vddarm;

    /* switch to ldo_bypass mode */

    if (ldo_bypass) {

        prep_anatop_bypass();

       /* decrease VDDARM to 1.275V */

        if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {

            printf("Read SW1AB error!\n");

            return;

        }

        value &= ~0x3f;

        value |= PFUZE100_SW1ABC_SETP(12750);

        if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {

            printf("Set SW1AB error!\n");

            return;

        }

        /* decrease VDDSOC to 1.3V */

        if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {

            printf("Read SW1C error!\n");

            return;

        }

        value &= ~0x3f;

        value |= PFUZE100_SW1ABC_SETP(13000);

        if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {

            printf("Set SW1C error!\n");

            return;

        }

        is_400M = set_anatop_bypass(1);

        if (is_400M)

            vddarm = PFUZE100_SW1ABC_SETP(10750);

        else

            vddarm = PFUZE100_SW1ABC_SETP(11750);

        if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {

            printf("Read SW1AB error!\n");

            return;

        }

BR,

N.S

[igorpadykov]

Hi Nori

if this is for a short time, seems this could be acceptable.

Best regards

igor

[norishinozaki]

Igor,

I see.

However considering ripple of something, you would like to suggest having little more margins, for example 1.250V.

Correct?

BR,

NS.

[igorpadykov]

Hi Nori

I agree with you, more margin is preferable.

Best regards

igor

[igorpadykov]

Hi Nori

>Do you think it's Ok to set it to 1.275V which looks well meeting the target range 1.225 - 1.3V?

it is not good as MMPF0100 SW1 accuracy is 25mV, according to

Table 54. SW1A/B/C Electrical Characteristics MMPF0100 datasheet.

Best regards

igor

[norishinozaki]

Hello Igor,

I don't understand why MMPF0100 SW1's 25mV accuracy is related to setting 1.275V VDD_SOC_IN.

The VDD_SOC_IN range is 1.225 - 1.3V in LDO Bypassed and the original u-boot setting is 1.3V.

Is it related to a gap between min V in LDO Enabled (1.350V) and max V in LDO Bypassed (1.30V).

Setting 1.275V increases the gap more.

Is that the reason u-boot is using max V(1.3V) in order to minimize the gap from 1.350V?

BR,

N.S.

[igorpadykov]

Hi Nori

>I don't understand why MMPF0100 SW1's 25mV accuracy is related to setting 1.275V VDD_SOC_IN.

Run mode: LDO bypassed : VDD_ARM_IN/VDD_SOC_IN max. is 1.3V

according to Table 6. Operating Ranges i.MX6DQ Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

so setting MMPF0100 1.275V with 25mV accuracy setting is not good .

Best regards

igor

[igorpadykov]

Hi Nori

>Why do we need to downgrade to 400MHz?

in bypass mode VDDARM_IN=1.150-1.3V

To change from ldo mode to bypass mode it is

better with changing to VDDARM_IN=1.175-1.5V

and set point VDDARM_CAP=1.125 V (396MHz operation).

After that change from ldo on mode to bypass.

Note, there may be other ways to achieve that.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[norishinozaki]

Hello Igor,

Thanks, but why "better with changing to VDDARM_IN=1.175-1.5V" ?

If you mean it "better to change gradually", I can understand it in case of i.MX6DL as you showed.

I'd like to know a case of i.MX6Q below.

From above u-boot code, in case of i.MX6Q we need to go 1.1V staying with LDO Enabled first.

* VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)

LDO_ARM need to have 0.975V then VDDARM_IN needs to be 1.1V in LDO Bypass.

So ARM needs to downgrade to 400MHz.

But why it cannot go to 1.150V in LDO Bypass directly?

BR,

N.S.

[igorpadykov]

Hi Nori

because these voltages are the same (very close) to 1.150-1.3V ldo bypass mode.

I think your understanding is correct but I could not understood what is your idea in :

"why it cannot go to 1.150V in LDO Bypass directly"

As I said there may be other ways to achieve that.

Best regards

igor

[norishinozaki]

Hello Igor,

I meant, without going to an intermediate state, without downgrading to 400Hz, just switch from LDO Enabled 1.275-1.5V to LDO Bypassed 1.150-1.3V range with keeping 800MHz.

Is this included in the other ways you meant?

BR,

N.S.

[igorpadykov · Accepted solution]

Hi Nori

without going to an intermediate state, LDO Bypassed 1.3V high limit may be

exceeded, as low limit LDO Enabled  = 1.275V.

So for safety reasons and having good margin, it is better to go to intermediate state.

Best regards

igor

[norishinozaki]

Igor,

I see, thanks!

Changing ARM frequencies, we just need to set LDO_ARM by bits in PMU_REG_CORE register per 25mV, right?

BTW, I found you comment in other thread.

"When ldo bypass (by default LDO bypass is enabled.) is used then after reset processor will start with lower power supply voltages, than needed."

Does this mean that SabreSDP starts with 400MHz?

I thought it starts with 800MHz in LDO Enabled and needs to go 400MHz in order to finally get to LDO Bypass at 800MHz.

BR,

NS.

[igorpadykov]

Hi Nori

>Changing ARM frequencies, we just need to set LDO_ARM by bits in PMU_REG_CORE register per 25mV, right?

yes

>I thought it starts with 800MHz in LDO Enabled and needs to go 400MHz in order to finally get to LDO Bypass at 800MHz.

right

Best regards

igor

[norishinozaki]

Hi Igor,

Thanks,

>Changing ARM frequencies, we just need to set LDO_ARM by bits in PMU_REG_CORE register per 25mV, right?

We also need to set ARM clock in half by CCRM_CACRR register, though.

Now we are going to switch to LDO Bypass.

Before that, we have to increase VDD_SOC_IN to 1.3V which is max V for LDO Bypassed VDD_SOC_IN range.

Do you think it's Ok to set it to 1.275V which looks well meeting the target range 1.225 - 1.3V?

BR,

N.S.