i.MX6Q 2 channel LVDS Clock Frequency

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i.MX6Q 2 channel LVDS Clock Frequency

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Contributor II

Hello,

I want to drive 1920x720 @60hz LCD monitor with i.mx6q with my custom designed board. LCD requires typical 90 MHz LVDS DCLK.

I know i should use LDB in split mode. What confuses me is the clock frequency. Can i.mx6q drive 90 MHz LVDS clock for 2 channel LVDS at the resolution of 1920x720 @60hz?

Second question is that my LCD panel 2 channel LVDS interface, one channel for odd pixels and second channel for even pixels?

Do i have to connect the imx6 LVDS0 pins to odd channel of LCD and imx6 LVDS1 pins to even channel of LCD or vica versa?

Thanks..

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Contributor II

Could you please verify that imx6q can drive 90 MHz clock on both LVDC0_CLK_P/N and LVDS1_CLK_P/N pads in split mode (both LVDS0 and LVDS1 signals are used)? This is a requirement for our LCD at 1920x720 @60 Hz.

The terminalogy in reference manuel really confuses me.

Could you verify this? Thanks 

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NXP TechSupport
NXP TechSupport

"LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @
60 frames per second, data rate supported up to 170 MHz)."

from sect.39.4.1 Input Parallel Display Ports i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards
igor

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Contributor II

Hello Igor,

Thanks for the reply.

"LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @
60 frames per second, data rate supported up to 170 MHz)."

This sentence is unclear to me.

Is "up to 170 MHz clock" the lvds clock driven out of cpu? I need to give 90 MHz lvds clock signal to LCD.

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NXP TechSupport
NXP TechSupport

Hi Mehmet

this is lvds clock signal to LCD.

Best regards
igor

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NXP TechSupport
NXP TechSupport

Hi Mehmet

yes it can drive, frequency details can be found in sect.39.4.1 Input Parallel Display Ports

and connections in Table 39-5. Channel Mapping

i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards
igor
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Contributor II

Hello Igor,

Thanks for the reply. I already checked the RM before opening this topic but i have unclear issues.

Table 39-5 mentions LVDS Channel 0  is mapped to DI0 first pixel, LVDS Channel 1 i mapped to DI0 second pixel.

What does it mean by first and second pixel? Does first pixel mean odd pixels, second pixel mean even pixels?

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NXP TechSupport
NXP TechSupport

>Does first pixel mean odd pixels, second pixel mean even pixels?

yes

Best regards
igor

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