i.MX6DQ PLL2 spread spectrum.

[satoshishimoda]

Hi community,

I want to confirm about i.MX6DQ PLL spread spectrum.

Please see my questions below.

[Q1]

Please see chapter 18.5.1.3.3 in IMX6DQRM Rev.1.

According to the explanation, I understand the PLL2 spread spectrum is "down spread".

Is my understanding correct?

[Q2]

I want to confirm how to set the spread spectrum.

If I use 528MHz PLL2 output for DDR and use -1% down spread, I have to set "Spread spectrum range" in a formula of chapter 18.5.1.3.3 to "5.28" MHz.

Is my understanding correct?

[Q3]

In chapter 18.5.1.3.3, "Modulation frequency" = (Fref x CCM_ANALOG_PLL_SYS_SS[STEP]) / (2 x CCM_ANALOG_PLL_SYS_SS[STOP]).

And, in chapter 18.7.5, "Frequency change step" = 24 x step / CCM_ANALOG_PLL_SYS_DENOM[B].

According to these formula, I understand there is a relationship between "Frequency change step" and "Modulation frequency" because both formula use CCM_ANALOG_PLL_SYS_SS[STEP].

And I set "CCM_ANALOG_PLL_SS[STEP] value larger, the cycle of modulation frequency will be faster.

Is my understanding correct?

Best Regards,

Satoshi Shimoda

[satoshishimoda]

I tested spread spectrum setting.

Then, I confirmed spread spectrum works correctly with the following setting.

DENOM : 50000(d)

STOP: 500(d)

STEP : 1(d)

And if I set "Frequency change step" in chapter 18.7.5 to 5.28 MHz when PLL2 output is 528MHz, the spreading was too large.

According to these result, I feel I have to set "Frequency change step" in chapter 18.7.5 to 1% of 24MHz (Fref) if I need -1% down spread.

Is this right?

Best Regards,

Satoshi Shimoda

[alfred_liu]

I can take the setting of one of our customer as the reference for you.

they set the Frequency change step about (1/1000)*24M for DDR 528MhZ, it works well.

[alfred_liu]

Hi, Satoshi

the "step" setting in register depends on the modulation frequency, which should be in the requirement of external devices, for instance, DDR chips genarallly tolerate 20k~60k modulation frequency.

[YixingKong · Accepted solution]

Satoshi

Here is the answers from our engineer. Please see if you have any further issues, and respond promotly.

Thanks,

Yixing

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[Q1]

Please see chapter 18.5.1.3.3 in IMX6DQRM Rev.1.

According to the explanation, I understand the PLL2 spread spectrum is "down spread".

Is my understanding correct?

A1: yes ,you are right.

for example if you want spread spectrum 9MHz on 400MHz frequency, the range will be 391MHz ~ 400MHz.

[Q2]

I want to confirm how to set the spread spectrum.

If I use 528MHz PLL2 output for DDR and use -1% down spread, I have to set "Spread spectrum range" in a formula of

chapter 18.5.1.3.3 to "5.28" MHz.

Is my understanding correct?

A2: yes ,you are right.

[Q3]

In chapter 18.5.1.3.3, "Modulation frequency" = (Fref x CCM_ANALOG_PLL_SYS_SS[STEP]) / (2 x CCM_ANALOG_PLL_SYS_SS[STOP]).

And, in chapter 18.7.5, "Frequency change step" = 24 x step / CCM_ANALOG_PLL_SYS_DENOM[B].

According to these formula, I understand there is a relationship between "Frequency change step" and "Modulation

frequency" because both formula use CCM_ANALOG_PLL_SYS_SS[STEP].

And I set "CCM_ANALOG_PLL_SS[STEP] value larger, the cycle of modulation frequency will be faster.

Is my understanding correct?

A3: yes ,you are right.

[vansreng]

Hi,

I have a couple follow-up questions related to this post and was wondering if you could help answer them:

1) Since the PLL2 operating clock freq is at 528 MHz, are we then applying spread spectrum to this center freq of 528 MHz and not the parent, fundamental clock freq of 24 MHz (assuming this is the external crystal oscillator that the IMX6 main board uses to derive its clock(s) from)?  As such, any harmonics of the 24 MHz observed below 528 MHz will not be affected by the spreading of the clock spectrum - ie: their amplitude will not be reduced?

2) Please help explain these two variables with examples on how their values setting could affect the clock signal integrity or operation:  CCM_ANALOG_PLL_SYS_SS[STOP], CCM_ANALOG_PLL_SYS_DENOM[B] (however, I understand the meaning of this one: CCM_ANALOG_PLL_SYS_SS[STEP]).  After reading the IMX6S reference manual, I still do not understand their meanings.  

3)  I'm currently seeing harmonics that are multiple of 24 MHz (which is my external crystal oscillator clock source).  These harmonics are pretty pronounced at higher frequencies above 500 MHz, will applying spread spectrum on PLL2 help towards reducing these harmonic amplitude levels?  Similar to question 1) above.

Any feedback to the above would be much appreciated.  

Thanks!

Van