i.MX6DQ MMDC self-refresh mode and DDR clock.

[satoshishimoda]

Hi community,

Our partner have a question about i.MX6DQ DDR3.

The partner want to keep DDR3 clock output, but in default DDR3 clock is stop for lower power consumption.

Please see "Power saving" feature in Table 44-1 of IMX6DQRM (Rev.2).

It says "• During self-refresh mode the clock (CK) that is driven to the DDR device will be gated for power saving." and "• In automatic self-refresh, the internal operating clock will be gated for power saving."

So I guess DDR3 clock is kept if user prevent entering to self-refresh mode.

Is this correct?

If correct, would you let me know how to disable auto self-refresh mode?

Best Regards,

Satoshi Shimoda

[art · Accepted solution]

Q. I guess DDR3 clock is kept if user prevent entering to self-refresh mode. Is this correct?

A. Yes, this is correct.

Q. How to disable auto self-refresh mode?

A. Generally, it depends on the software, running on the processor, since MMDC puts an external memory to self-refresh mode and restores it back under the software control (or by hardware request from the clock/power management module, that is also controlled by software). So, the general recommendation is to

disable entering the low-power modes in software (e.g. in OS, running on the processor).

Have a great day,
Artur

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[Yuri]

You may try to set MMDCx_MAPSR [PSD] bit. But - I am afraid - this

does not prevent automatic entering self-refresh mode when

i.MX6 is in LPMD (Low Power Mode).

Have a great day,
Yuri

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