i.MX6DQ Fly-by topology with 8 DDR3 memories.

[satoshishimoda]

Hi community,

Our customer have a question about i.MX6DQ DDR design.

Please see Figure 3-9 in i.MX6 Hardware Development Guide (IMX6DQ6SDLHDG Rev.1).

We understand that this figure shows the reference layout of the decoupling capacitor with 4 DDR3 memories for T-topology.

Also reference board schematics show how much capacitance is needed with 4 chips DDR3 design for T-topology.

Actually, our customer will design i.MX6DQ platform with Fly-by-topology with 8 DDR3 memories.

So would you give us your advice about placement of decoupling capacitor similar as Figure 3-9, and how much capacitance is needed in this case?

Best Regards,

Satoshi Shimoda

[art · Accepted solution]

Regardless of the routing topology, the common decoupling caps placement rule is as follows: there should be one 0.22uF decoupling capacitor per power pin, the capacitors should be located as close to the pins as possible. In case of placement room limitation, the neighbour (located next to each other) power pins can share a single decoupling capacitor.

Have a great day,
Artur

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[satoshishimoda]

Dear Artur,

Thank you for your reply.

We understood how should we place the decoupling capacitors.

Then, our customer have one more question.

They feel 22uF capacitors like as C35, C36 on i.MX6DQ SABRE SDP are not needed if enough 0.22uF decoupling capacitors are placed as you said.

But I think 22uF capacitors are needed even if there are enough 0.22uF decoupling capacitors since the 22uF capacitors are bulk capacitor for low frequency impedance.

Which understanding is correct?

Best Regards,

Satoshi Shimoda

[art]

Dear Satoshi,

You are right, the 22uF capacitors are still required, at least one capacitor per DDR chip.

Best Regards,

Artur