i.MX6DQ EIM data latch timing in async read access.

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i.MX6DQ EIM data latch timing in async read access.

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Senior Contributor I

Hi community,

We have some question about i.MX6Q EIM timing when it is in asynchronous read access.

We heard the latch timing of async read access is on the falling edge of a half clock before end of access in past.

Is this correct?

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

  Data are latched at the recent rising edge (of internal clock) before
OE or CS going HIGH (inactive) ; whoever comes first.

Please refer to end of access point below.

EIM_read.jpg


Have a great day,
Yuri

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NXP TechSupport
NXP TechSupport

  Data are latched at the recent rising edge (of internal clock) before
OE or CS going HIGH (inactive) ; whoever comes first.

Please refer to end of access point below.

EIM_read.jpg


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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Senior Contributor I

Hi Yuri,

I confirmed OE and CS negate timing is a rising edge of internal clock.

I think in the case of Figure 18, the trigger for OE and CE negation is the rising edge called "end of access".

Then, data latch timing is one more previous rising edge of "end of access"? or latched on the "end of access"?

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

latched on the "end of access".

Regards,

Yuri.