i.MX6DQ DI0_CLK_PERIOD_x

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i.MX6DQ DI0_CLK_PERIOD_x

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sugiyamatoshihi
Contributor V

Hi,

I'd like to confirm clock source of these clocks.

DI0_CLK_PERIOD_0 and DI0_DISP_CLK_PERIOD

This IPUx_PM field descriptions in i.MX6DQ Reference manual describes about DI0_CLK_PERIOD_x

1. Which IPUx_DI0_CLK_ROOT or IPUx_HSP_CLK_ROOT is for Fast_freq?

2. Does Target_freq mean DI0_CLK_PERIOD or DI0_DISP_CLK_PERIOD? 

3. Does IPUx_HSP_CLK_ROOT derive to both DI0_CLK_PERIOD and DI0_DISP_CLK_PERIOD?

di0_clk_period1.jpg

di0_dis_clk_period1.jpg

Best Regards,

Sugiyama

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 

  Generally parameters DI0_CLK_PERIOD and DI0_DISP_CLK_PERIOD

relate to the same entity - display clock. DI0_DISP_CLK_PERIOD is used

in fine (display) pulses generation, where such pulse parameters, as length

(PERIOD), first edge location (UP) and second edge location (DOWN) are

defined, assuming the HSP clock.

  The DIx_CLK_PERIOD_1 and DIx_CLK_PERIOD_0 are designed for display

frequency changing between two modes (1 and 0). Here target frequency 1
and target frequency 2 are used. They are normalized to maximal possible

frequency ( so called fast_freq).

Have a great day,

Yuri

 

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