i.MX6DQ DDR parameters (tIS, tsr).

[satoshishimoda]

Hi community,

Our partner have some questions about i.MX6DQ DDR parameter.

Please see their questions as below.

[Q1]

Please see Table 42 of IMX6DQCEC Rev.4, they want to know the condition to apply DDR4 and DDR6 parameter.

When set drive impedance to largest value, in other words when wafeform becomes degrade and tsr value is smallest, DDR4 satisfies 500ps (min) also?

If not, would you let us know the drive impedance and the tsr (max, min) value to satisfy tIS=500ps (min)?

[Q2]

Please see Table 30 in IMX6DQCEC Rev.4, tsr value is shown as the condition Drive impedance = 34 ohm.

However, i.MX6DQ can set the drive impedance to other values as following in IMX6DQRM Rev.3 (e.g. chapter 36.4.463)

  240 ohm, 120 ohm, 80 ohm, 60 ohm, 48 ohm, 40 ohm

So would you let me know the tsr value when drive impedance is set to the above values also?

Best Regards,

Satoshi Shimoda

[BiyongSUN]

i.MX6 DDR Stress Test Tool
https://community.freescale.com/docs/DOC-96412

i.Mx6DQSDL DDR3 Script Aid
https://community.freescale.com/docs/DOC-94917

Freescale i.MX6 DRAM Port Application Guide-DDR3
https://community.freescale.com/docs/DOC-101708

[igorpadykov]

Hi Satoshi

1.>When set drive impedance to largest value, in other words when wafeform becomes

>degrade and tsr value is smallest, DDR4 satisfies 500ps (min) also?

yes, DDR4 should be satisfied for customer board, however this depends on customer

board layout. One can use ibis modelling for such purposes.

>would you let us know the drive impedance and the tsr (max, min) value to satisfy tIS=500ps (min)?

since this depends on specific board layout, it is not possible to provide such data.

It is necessary to find optimal drive impedances for customer board himself, which would

satisfy tIS=500ps (min).

2. unfortunately tsr value is not specified for other drive impedances.

For estimation purposes one can calculate himself it using model Figure 9.

Best regards

igor

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[satoshishimoda]

Dear Igor,

Thank you for your reply.

> yes, DDR4 should be satisfied for customer board, however this depends on customer

> board layout. One can use ibis modelling for such purposes.

I think the tIS value which should be satisfied on a DDR pad of a customer board is not 500 ps (min), it should be tIS (total) = tIS (base) + delta tIS as written in JEDEC standard.

Is this correct?

I understood DDR4 value is the minimal time between DRAM_SDCLKx_P positive edge and negative edge of DRAM_CS_B, DRAM_RAS_B, DRAM_CAS_B, or positive edged of DRAM_SDEW_B, DRAM_ODTx, DRAM_SDCKEx on the i.MX6 pads.

For example, when AC175, DDR3-800, CMD/ADD Slew rate = 2.0 V/ns, CK,CK# Differential Slew Rate = 2.0 V/ns,

tIS (base) is 200 ps and delta tIS is 88 ps as written in JEDEC standard.

So tIS (total) = 200 ps + 88 ps = 288 ps.

In this case, i.MX6 output tIS = 500 ps (min) on the i.MX6 pads.

To satisfy JEDEC standard, the skew among output from i.MX6 pads and input to DDR pads on a customer board is allowed up to 212 ps (500 ps - 288 ps).

Is my understanding correct?

Then, I think my question is about the tIS value on the i.MX6 pads, not on the DDR pads, so it is not affected by board layout.

IBIS file provides the slew rate with each drive impedance, but not provided how tIS value on the i.MX6 pad is affected by drive impedance and slew rate, right?

So we want to know how tIS value on the i.MX6 pad is affected by drive impedance and slew rate.

In other words, we want to know how allowed skew on a custom board is changed by variation of drive impedance and slew rate.

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

I think your understanding is right.

Regarding "how tIS value on the i.MX6 pad is affected by drive impedance and slew rate."

- unfortunately such parameters are not given in datasheet and they are not

characterized. I would suggest to apply to local FAE channel for requesting

possibility that such data were produced for you.

Best regards

igor