i.MX6DL - PCIe issue after WDG reset

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i.MX6DL - PCIe issue after WDG reset

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christian_neuwi
Contributor III

Hi,

we're building our own hardware based on an i.MX6DL and recently ran into a PCIe issue, which is accurately described here (our Kernel version is v4.1.15, though). The work-around proposed in one of the following entries of this thread (i.e. clear the PCIe-related flags in GPR1 and GPR12 in the bootloader; see here) appears to fix this issue.

Can you confirm that this is a valid work-around?

Furthermore, this raises the question if there are any other registers or components in the SoC that are not cleared/reset after a WDG reset as opposed to a POR.

Can you provide some information on that?

Thanks,

Chris.

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art
NXP TechSupport
NXP TechSupport

Yes, this workaround is valid.

Best Regards,

Artur

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art
NXP TechSupport
NXP TechSupport

1. Since the watchdog reset is a kind of Warm reset, the issue you observe looks like the effect of the ERR008587 silicon erratum, described in the i.MX6Dual/Quad Silicon Errata Rev.6.1 document:

https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf

It is described for i.MX6Dual/Quad, but seems to be applicable to i.MX6DualLite as well, since the PCIe interface modules of all these processors are identical.

2. Please refer to the Section 60.6.1.1 "Reset inputs and outputs" of the i.MX6Solo/DualLite Reference Manual Rev.3 document:

https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf

As it states, the WDOG reset, as opposed to POR, does not affect the ARM core Power-On Reset (that is not the same as the ARM core Soft Reset that the WDOG reset triggers on), ARM core Debug module reset, Secure JTAG Controller (SJC) reset and Secure Real-Time Counter (SRTC) reset.


Have a great day,
Artur

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christian_neuwi
Contributor III

Thanks for your answers, Artur.

However, I don't think that ERR008587 describes the issue we're seeing, because it doesn't happen rarely. In fact, this issue is 100% reproducible as it happens each and every time the i.MX6 goes through a watchdog reset while the PCIe core is enabled. It appears as if the PCIe-related flags in GPR1 and GPR12 are 'merely' not cleared, hence don't reflect the actual state of the PCIe core in such a case.

The workaround suggested in ERR008587 might be similar, but cannot be applied when a 'real' watchdog reset occurs.

As such, I ask again:
Is clearing the PCIe-related flags in GPR1 and GPR12 in the bootloader a valid workaround for this issue?

Thanks,

Chris.

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art
NXP TechSupport
NXP TechSupport

Yes, this workaround is valid.

Best Regards,

Artur