i.MX6DL DDR register setting value by .inc file in DDR stress tester.

[satoshishimoda]

Hi community,

We have two questions about DDR Stress Test in https://community.freescale.com/docs/DOC-96412#.

I think it is better to post this question in https://community.freescale.com/docs/DOC-96412#, but I could not post a comment.

Anyway, please see our questions as following.

[Q1]

Please see IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET setting value in MX6DL_SabreSD_DDR3_register_programming_aid_v1.5.inc.

It is "setmem /32 0x020e0494 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET".

Next, please see chapter 37.4.289 (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) in IMX6SDLRM (Rev.1).

According to the setting value in the .inc file, DDR_SEL is set to "RESERVED0", not "DDR3".

Is this no problem?

If it is no problem, would you let me know why it is set to "RESERVED0"?

[Q2]

Please see IOMUXC_SW_PAD_CTL_GRP_DDRMODE setting value in MX6DL_SabreSD_DDR3_register_programming_aid_v1.5.inc.

It is "setmem /32 0x020e0760 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE".

Next, please see chapter 37.4.464 (IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL) in IMX6SDLRM (Rev.1).

According to the setting value in the .inc file, DDR_INPUT is set to "DIFFERENTIAL" even though DRAM_DATAxx signals are not differential.

Is it no problem?

If it is no problem, would you let me know why it is set to "DIFFERENTIAL?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

1. Correct DDR_SEL=00 DDR3_LPDDR2 — DDR3 and LPDDR2 mode.

is given in latest sect.36.4.347 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET)

IMX6DQRM i.MX 6Dual/6Quad Applications Processor Reference Manual.

Next revision i.MX6SDL RM also will be changed.

2.  Yes you are correct: DDR_INPUT should be set to "DIFFERENTIAL", because

according to description in RM:

"Select one of next values for group: .

Affected pads: DRAM_SDQS0_P, DRAM_SDQS1_P, DRAM_SDQS2_P, DRAM_SDQS3_P,

DRAM_SDQS4_P, DRAM_SDQS5_P, DRAM_SDQS6_P, DRAM_SDQS7_P"

By definition these signals are differential.

In general there is no much error in setting this (and other signals) to either option:

CMOS input mode expects signals to rise above 80% for high readings

and fall below 20% for low readings.

In differential mode signals only have to cross over the VREF (50%) level,

to be counted as high or low. Also this mode requires more power.

So for example in noisy board one can try to choose CMOS input mode even

for differential signals, thus improving noise resistance and decreasing power consumption

(and associated with it board noise).

Best regards

igor

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[satoshishimoda]

Hi Igor,

> 2.

> In general there is no much error in setting this (and other signals) to either option:

According the reply, I understood either option is no problem.

Then, which is freescale's recommendation?

Or no recommendation and user select it free?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

one can use values provided by

DDR Stress Test tool.

Best regards

igor