i.MX6 solo resume from Deep sleep mode

[Ajesh_Ametek1]

Hi,

We have a custom board based on i.MX6 Solo with below specs:

HW Configuration:  PMIC- MMPF0100NPAZES, 4Gb DDR3(MT41J128M16HA-15E:Dx 2), 32Gb EMMC(EMMC04G-W627-X02U)

We are following same decoupling scheme as followed in SABRE-AI CPU card.

Kernel version and/or BSP release used = based on Linux 6.1.1_1.0.0

We are facing a problem in which iMX6S fail to resume normally from suspend mode (DSM).

We checked the board could work  normally before DSM. But once it went to DSM, it cannot resume anymore unless power cycle. It does not lock up every time it wake up from deep sleep. So the issue is random.

We had observed that  if we don’t assert VSTBY(PMIC_STBY) signal to the PMIC, the iMX6S is able to resume from DSM always.

Below are some of the iterations we tried

1. If keep VDD_ARM_IN at 1.375V(instead of 0.975V set by default driver ) in DSM, we saw an improvement. Earlier failure rate was 1 in 5 times. With VDD_ARM_IN change, failure rate is 1 in 50 times.
2. We tried to apply errata ERR005852(Analog: Transition from Deep Sleep Mode to LDO Bypass Mode may cause the slow response of the VDDARM_CAP output).  When we tried this, we saw system was crashing after wake up.
3. We had checked PMIC_STBY_REQ  signal and found that signal is ‘high’ in deep sleep mode and ‘low’ in wake up condition(when wake up issue occurred as well). This points that i.MX6 is trying to wake up, but getting stuck later.
4. We have verified that this happens with the default Power management driver itself and the system was not waking with console as wakeup source.

Please let us know whether BSP 6.1.1_1.0.0 has the fix for ERR005852 already.

Please let us know possible causes for this issue and provide suggestions for fixing the same.

[Ajesh_Ametek1]

Hi Sanket,

Thank you for your response...

We had verified that PMIC_STBY_REQ is de-asserted after wake up even during a failure condition.

We have provided same values and number of decoupling capacitors as mentioned in HW development guide.

[Sanket_Parekh]

Hi @Ajesh_Ametek1 

I hope you are doing well

As mentioned in section 18.5.3 Power modes of the reference manual IMX6SDLRM, Please check 

-> All cores are in WFI

->SCU is in idle mode, 
-> And the L2 cache is in idle mode,

Please share your observations for the same.

Thanks & Regards

Sanket Parekh

[Sanket_Parekh]

Hi @Ajesh_Ametek1,

I hope you are doing well

The PMIC_STBY_REQ pin is controlled by the VSTBY bit and DSM mode. 

Kindly confirm whether the SoC is exited from standby mode or not using the information from Figure 60-2. Chip reset scheme under external PMIC control in the Reference Manual IMX6SDLRM

It is mentioned on page no. 858 of Reference Manual.

"NOTE: When returning from stop mode, the PMIC_STBY_REQ will be de-asserted (if it was asserted
when entering stop mode). See stby_count bits."

For the information related to the errata ERR005852 workaround kindly refer to the below link.

https://community.nxp.com/t5/i-MX-Processors/About-Errata-ERR005852-in-i-MX6DL/td-p/360990

For more information please refer to Table 2-6. Power and decouple recommendations from the Hardware Development Guide IMX6DQ6SDLHDG

Thanks & Regards,
Sanket Parekh