Hi Qiang Li:
sorry for bother you.
I have a issue same as below case 1,
we use i.mx6 bt.656 (d0~ d7) + CLK output to tw8836 (d0 ~ d7) CLK,
no swap pin.
issue screen:
when we output white line to display , and the line will Flashing.
we want to send 720*480@60hzNTSC(480i) resolution.
The Techwell vendor said , imx6 sent twice EAV , not send SAV + EAV.
(1)Does the driver setting incorrect?
(2)HW how to vertify the waveform by scope?
where can i get the sample waveform for reference?
thank you so much.
darren_wang@compal.com i.MX6 bt656 display interface"
1, Using no external HSYNC/VSYNC, just with BT656 itself . iMX6S can not send correct BT656 signal to AK8817
source like bellow"
But here I have a problem about the patch into iMX6S customer board with AK8817 encoder chip.
1, Using no external HSYNC/VSYNC, just with BT656 itself . iMX6S can not send correct BT656 signal to AK8817
source like bellow
//-----------------------------------------------------------------------------------
/driver/video/mxc/mxc_bt656if.c
static struct fb_videomode bt656if_modedb[] = {
{
/* NTSC Interlaced output */
"BT656-NTSC", 60, 720, 480, 37037,
19, 3,
20, 3,
276, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED,
FB_MODE_IS_DETAILED,},
......
......
};
//------------------------------------------------------------------------------------
/drivers/mxc/ipu3/ipu_disp.c
/* COUNTER_2: HSYNC for each line */
/* COUNTER_2: HSYNC for each line */
_ipu_di_sync_config(ipu,
disp, /* display */
DI_BT656_SYNC_HSYNC, /* counter */
h_total - 1, /* run count */
DI_SYNC_CLK, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
2*div /* COUNT DOWN */
);
/* COUNTER_3: internal VSYNC for each frame */
_ipu_di_sync_config(ipu,
disp, /* display */
DI_BT656_SYNC_IVSYNC, /* counter */
v_total - 1, /* run count */
DI_BT656_SYNC_HSYNC, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);