i.MX6 solo IPU clock relationship

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i.MX6 solo IPU clock relationship

Contributor III

Dear friends,

I still have troble to have TFT panel works although I can change the display color. I am afraid that the control signals are not synchronized or correctly generated for the iMX 6 solo processor.

I can not get any useful information from IPU RM. I have a few questions here:

1. What are the relations between IPU1_HSP_CLK_ROOT, IPU1_DI0_CLK_ROOT, and LDB_DI0_IPU?

2. What does ipp refer to in the RM? Does it refer to external? that is, ipp_di0_clk comes from external?

3. is the DI interface clock derived from IPU1_HSP_CLK ro from IPU1_DIx_CLK_ROOT?

4. there is a register to select counters for Hsync and Vsync, but how does these signals mapped to pin1-pin7?

5. Is the IPU1_DI0_CLK_ROOT used to for BASE TIMER?

I Have not routed pin1-pin15 out, so I can not observe these signals.


thank you very much




a little bit confused in the following paragraph in RM

The DI clock can be derived from IPU's clock (HSP_CLK) or from an external source
(via the DIn_DISP_CLK - ipp_di_#_ext_clk pin). The clock's source is statically selected
by configuring the DI#_CLK_EXT bit.


here what does DI clock refer to? interface clock? or the clock used to generate BASE CLOCK?

what dose DIn_DISP_CLK - ipp_di_#_ext_clk refer to?  Does it refer to DIx_DISP_CLK? I can not find any ipp_di_#_ext_clk term in any other place.


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3 Replies

NXP TechSupport
NXP TechSupport
1) they are all ipu clocks, you can refer to the Table 38-7. IPU Clocks of reference manual

2)for the ipp_di0_clk:
Alt2 of pin EIM_DA14 weim.WEIM_DA_A[14] ipu1.DI1_D1_CS ccm.DI0_EXT_CLK

3) 240 Mega-Accesses/Sec if the DI clock is derived from an external to IPU source
(like another PLL)
• 264 Mega-Accesses/Sec if the DI clock is derived from the IPU clock (HSP_CLK)

so the DI clock is from external or HSP_CLK

4) I don't know what you mean, what register and what PIN1-PIN7

5) what pin1-pin15 do you mean? do you mean DIX_PIN? could you observe the ipu clock?




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Contributor III

Dear Joan,

you are right, by pin1-pin15 I mean the DI_pinx in Fig38-39. I tried different IPU_CLK value in SDK code, now I can display R,G,B,yellow,pink, etc,strips on the panel. Because I don't know the exact relationship between these clocks, so I just tried different values to see how it works.

the IPU chapter in RM is a little confused, I can not figured out the purpose of every clock.

Now I get one idea, the external means external to IPU, ^_^.

It seems to me that the active clock start point and active line start point both use fixed counter (counter 4 and 5), Am I right?

thanks again very much,


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NXP TechSupport
NXP TechSupport

yes, you are right, you can choose different Divider from the register


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