i.MX6: power reset vs SRC rest

[vsiles]

From the i.MX6 Firmware guide:

Once it has been released from reset, each Cortex-A9 core attempts to execute at the
ARM reset exception vector upon initial power-up. This vector in the chip memory map
(at 0000 0000h) is part of the on-chip boot ROM.

Does this apply to any kind of reset (watchdog, using SRC registers, power off, ...) or is it only when the board is powered on the first time ?

I'm trying to understand what would happen if a core (e.g. core 0) running in non secure mode tries to reset another core, which will then reset in secure mode.

Best,

V.

[igorpadykov · Accepted solution]

Hi Vincent

you are right  Cortex-A9 core ARM reset exception applies to

all kinds of reset, in particular one can check Chapter 60
System Reset Controller (SRC) i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor
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