Hi folks,
currently I'm working with SPI-NOR flash on i.MX6 board and faced with a strange issue. The default SPI clock is 30MHz, flash works good. The problem occures when I set SPI clock to 60MHz. At this frequency, the data collected in i.MX6 RX FIFO is shifted right for 1 bit. So, for example, if I send READ_ID command 0x9F, I should receive 0xC2 (and I do receive it at 30MHz), but at 60MHz I receive 0x61 at any time (0x61 = 0xC2 >> 1).
Moreover, I connected oscilloscope - the pictires for 30MHz and 60MHz are completely the same. So no physical deviations were observed.
Also, according to the flash spec - it supports up to 133MHz.
Is there any clock speed limitations or known HW errors in eCSPI on i.mx6 SoC?
With best regards,
Alex
Solved! Go to Solution.
Hello,Alex,
I remember MAX clock of eCSPI on i.mx6 is 52MHz, Please try !
Regards,
Weidong
Hello Alex,
Were you able to resolve the max clock speed issue?
We have also observed a hard limit of 30MHz clock. It could be the Freescale implementation of the Linux drivers. When ioctl() is used to set the clock, anything over 30MHz is accepted silently without errors and the clock is preset to 30MHz.
Regards,
Andrew
From i.MX6 Datasheet (IMX6DQCEC, Rev. 2.3, 07/2013),
Table 52 (ECSPI Master Mode Timing Parameters) :
ECSPIx_SCLK Cycle Time–Read
• Slow group 55 ns
• Fast group 40 ns
ECSPIx_SCLK Cycle Time–Write 15 ns
Hello,Alex,
I remember MAX clock of eCSPI on i.mx6 is 52MHz, Please try !
Regards,
Weidong
Hello,
thank you for the hint. :smileyhappy:
That's funny, but I see no possibility to set 52MHz. SPI clock is derived from PLL3. And according to the Reference Manual, PLL3 can be one of two: 480 or 524 MHz, also there is a static divider /8, so base eCSPI frequency is 60MHz or 66MHz. Due to we are able to use a whole dividers only, I see no way to derive something higher than 30MHz.
Another question. is there any point in RM or other documentation regarding this limitation?
Alex