Dear Sirs,
I am checking the i.MX6 Watchdog Timer module.
There is a Power-down counter in Watchdog Timer module.
The Power down counter with fixed timeout period of 16 seconds,
which if not disabled after reset will assert WDOG_B signal low.
This feature is intended to prevent the hanging up of core after reset,as WDOG is not enabled out of reset.
The WDOG_B signal is assigned at GPIO_9 [ALT1].
If the hanging up of core after reset is occurred,
the Pad Mux Register became default value by reset.
The WDOG_B signal function is not selected at GPIO_9 pin.
I think that I can not watch the WDOG_B signal low at GPIO_9 by Power-down counter timeout.
Is my understanding correct ?
Or, by existing the special path for the Power-down counter timeout ,
can I watch the WDOG_B signal low ?
Best Regards,
Koichi Sakagami
