i.MX6 VDDHIGH_IN power-up sequence

[carlosreverbel]

Hello,

   I am currently developing a board with the i.MX6 and I intend to use the PMIC MMPF0100F0 with its pre-programmed OTP configuration. I would like to know if it is possible to power the VDDHIGH_IN rail after powering VDDARM and VDDSOC power rails.

   As shown on the picture below, the SW2 (+3V3) is the 5th rail to power-up and I wonder if it can cause any problem while booting. 

   Thank you!

   

[gusarambula]

Hello Carlos Reverbel,

Please take a look at the following thread that may answer your question.

https://community.nxp.com/message/368363

If possible, I would recommend having VDDHIGH_IN and VDD_SNVS_IN powered first, to ensure that the constraints listed on the datasheet are meet.

I hope this helps,

Regards,

[carlosreverbel]

Hello!

   Thank you very much for your answer. Unfortunately I cannot access the link you sent...

[gusarambula]

My apologies.

Please find the information from the mentioned thread. There is an alternative on what you may do to optimize the power sequence although I strongly recommend changing your power sequence so VDD_VDD_HIGH_IN are applied at the same time.

" You are right, the PF0100 (F0) using may violate power up sequence.

   We can consider two options (assuming iMX6 with PF0100, no coin cell).

1.  VDD_SNVS_IN and VDD_HIGH_IN  should be connected with each other.

 In such case - I am afraid - we do not have proper output from the PF0100 to satisfy power up sequence

 (VDD_SNVS_IN should be applied first). So, optional LDO of 3V (LTC3025) is needed here to supply

 VDD_SNVS_IN and VDD_HIGH_IN. The PF0100 is not used to feed VDD_SNVS_IN and VDD_HIGH_IN.

2.

 VDD_SNVS_IN is connected to VSNVS of the PF0100.

 VDD_HIGH_IN is connected to VGEN5 of the PF0100, assuming F0 of  pre-programmed OTP, for 2.8V

   In any case when VDD_SNVS_IN != VDD_HIGH_IN some current (between VDD_SNVS_IN and VDD_HIGH_IN) will be observed it would be better to avoid such current when there is no a battery (which is intended  either for input or for output).  To minimize current effect, one can configure  VGEN5 of the PF0100 for 3.0V (in order VDD_SNVS_IN = VDD_HIGH_IN ) just after system starts."

I hope this helps!

Regards,

[carlosreverbel]

Hi, thank you very much!

   I decided to change the PMIC from PF0100 F0 to F4. With the new configuration, SW2  (3V15) turns on after the SNVS rail (and before CORE and SOC rails). SNVS and VDDHIGH_IN would not be connected together, SNVS would be powered first with 3V and VDDHIGH_IN afterwards with 3V15. After that, CORE and SOC rails would be powered at the same time. I thing with this new arrangement the board will boot with no problems and there will be no current leakage (no coin cell installed), is that correct? 

   I am only concerned about the 2V5 rail now, it comes from VGEN3 (disabled by default) and it powers NVCC_ENET, NVCC_RGMII and DVDDH of the ethernet PHY (KSZ9031). Is there any problem in starting the board with this power rail turned off and then turn it on while the bootloader is running?

Regards,

Carlos Reverbel