We are looking at designing around the ULL and utilizing the Win 10 IOT BSP. Design constraints have a lot to do with power consumption. We got the win 10 BSP running on the EVK but based on performance of the RAM viewing it through the Windows Device Portal it appears that the majority of the RAM is consumed. If we use the ULL we will need to expand the RAM to the maximum capability.
Per the ULL hardware development guide section 3.5:
"The chip can support up to 2 GB of DRAM memory. i.MX 6ULL DDR routing needs to be separated into
three groups: data, address, and control. Each group has its own method of routing from an i.MX 6 series chip to DDR memory. The DDR layout has 2 Gbyte and 1 Gbyte options."
How are these 2 options accomplished accomplished? I can find no examples in the developers guide, Community forum, or other online resources. Can I use 4 chips at 8Gb (512M x 16) or would we be limited to 2 chips at 16Gb (1G x 16)?
Should we look to another design guide for explanation (like the SoloX HW design guide)? Can we look at the other EVK's in the I/MX6 family for reference (SoloX, Quad)?
