i.MX6 ULL PowerUpSeuence

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i.MX6 ULL PowerUpSeuence

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mikitakashi
Contributor II

Please tell us about the following points in Power-Up Sequence of i.MX6ULL.

1. IMX6ULLIEC.pdf (DataSheet) has no sequence description for the following power supply.Would you mind thinking that there is no sequence order if it is after VDD_SNVS_IN?
-NVCC_DRAM
-NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD
-VDDA_ADC_3P3,ADC_VREFH

2. Is there any problem with the POWER UP sequence(Step) below?

Also, at Step 4, the NVCC (* 1) power supply is still OFF, but can not leak to the NVCC (* 1) power supply terminal (* 2)?
-Step1 : VDD_SNVS_IN (+3.3V)
-Step2 : VDD_HIGH_IN (+3.3V)
-Step3 : VDD_SOC_IN (+1.35V)
-Step4 : NVCC_DRAM (+1.35V)
-Step5 : NVCC(*1) / VDDA_ADC_3P3 / ADC_VREF(+3.3V)
(*1)NVCC : NVCC_GPIO,NVCC_UART,NVCC_ENET,NVCC_SD1,NVCC_NAND,NVCC_CSI,NVCC_LCD

(*2)e.g. GPIO1 , GPIO2 , GPIO3 , GPIO4 , GPIO5

Thanking you in advance.

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mikitakashi
Contributor II

Thank you very much.

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igorpadykov
NXP Employee
NXP Employee

Hi miki

1. all other power supplies can be powered up in any order after step

described in i.MX6ULL Datasheet sect.4.2.1 Power-Up Sequence:

"VDD_HIGH_IN should be turned on before VDD_SOC_IN."

2. this is correct power up sequence

Best regards
igor
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mikitakashi
Contributor II

Thank you very much.

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