i.MX6 UART connection.

[satoshishimoda]

Hi communty

I got a report that UART I/F on a custom board did not work well from our customer.

So I checked UART setting and connection.

Then, according to i.MX6: What does the DTE/DCE in i.MX6's UART do and how are RTS and CTS affected by the UARTxUFCR[DT..., I understood the UART4 connection as "uart4.pdf" sheet.

Is this correct?

Actually, the customer is using the connection described as "customer's connection" in the attached excel file.

If my understanding is correct, I think the customer should modify the connection as "Modification Plan" in the exel file.

Is this correct?

Best Regards,

Satoshi Shimoda

[satoshishimoda]

Sorry, I found my mistakes about modification plan.

The attache file "customer's connection2.xlsx" shows correct modification plan.

Best Regards,

Satoshi Shimoda

[YixingKong]

Satoshi

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

[satoshishimoda]

Hi Yixing Kong,

> Had your issue got resolved?

Yes, UART is working correctly now.

But I have not understand UART module well.

So could you give me a reply to my post on Apr 30?

Best Regards,

Satoshi Shimoda

[PeterChan · Accepted solution]

Hi Saroshi-san,

Attached table is the UART I/O configuration in different modes from i.MX6DQ datasheet. As you can see, the port functions are reversed between DCE and DTE mode.

By default, BSP always configures the UART to DCE mode.

From the table, RXD and RTS are the input ports to UART in DCE mode.

For instance, let us try to mux the UART4 to CSI0 port.

SW_MUX_CTL_PAD_CSI0_DATA12 =  ALT3 (UART4_TX_DATA)

SW_MUX_CTL_PAD_CSI0_DATA13  = ALT3 (UART4_RX_DATA)

SW_MUX_CTL_PAD_CSI0_DATA16  = ALT3 (UART4_RTS_B)

SW_MUX_CTL_PAD_CSI0_DATA17  = ALT3 (UART4_CTS_B)

In DCE mode, pad CSI0_DATA13(UART4_RX_DATA) & CSI0_DATA16(UART4_RTS_B) will be the input pads involving in Daisy chain. Thus,

UART4_UART_RX_DATA_SELECT_INPUT = 11b  (route UART4_RX_DATA to CSI0_DATA13)

UART4_UART_RTS_B_SELECT_INPUT = 0 (route UART4_RTS_B to CSI0_DATA16)

Thanks,

Peter

[ShawnBai]

Hello Peter,

Very useful infos.

And Now I'm working on the i.mx6 solo.

What I want to do with uart4 is to configure

CSI0_DAT13 to UART4_TXD

CSI0_DAT12 to UART4_RXD

  I've already done sth about it, but it seems not working as expected, Could you tell me how to do this?

And FYI as a comparation,

configure

CSI0_DAT13 to UART4_RXD

CSI0_DAT12 to UART4_TXD,

and just crossing the hardware wiring TXD/RXD between imx6 solo and the device works as expected.

Following is what I've already done to configure CSI0_DAT13 to UART4_TXD  and  CSI0_DAT12 to UART4_RXD.

With  the two pinmux in my board header file

    MX6DL_PAD_CSI0_DAT12__UART4_RXD,

    MX6DL_PAD_CSI0_DAT13__UART4_TXD,

And their definitions are

#define MX6DL_PAD_CSI0_DAT12__UART4_RXD                                        \

  IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, MX6DL_UART_PAD_CTRL)

#define MX6DL_PAD_CSI0_DAT13__UART4_TXD                                        \

  IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)

the log for running the function mxc_iomux_v3_setup_pad() in iomux-v3.c

/*

* configures a single pad in the iomuxer

*/

int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)

{

  u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;

  u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;

  u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;

  u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;

  u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;

  u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;

  if (mux_ctrl_ofs)

  __raw_writel(mux_mode, base + mux_ctrl_ofs);

  if (sel_input_ofs)

  __raw_writel(sel_input, base + sel_input_ofs);

  if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)

  __raw_writel(pad_ctrl, base + pad_ctrl_ofs);

    // dat12

    if ((pad_ctrl_ofs == 0x0368) || (pad_ctrl_ofs == 0x036C) || (pad_ctrl_ofs == 0x0378) ||(pad_ctrl_ofs == 0x037C))

        {

          if (mux_ctrl_ofs)

            printk("\n mux_ctrl_ofs(0x%x) mux_mode (0x%x) \n", mux_ctrl_ofs, mux_mode);

          if (sel_input_ofs)

            printk(" sel_input_ofs(0x%x) sel_input (0x%x) \n", sel_input_ofs, sel_input);

     if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)

            printk(" pad_ctrl_ofs(0x%x) pad_ctrl (0x%x) \n", pad_ctrl_ofs, pad_ctrl);

        }

  return 0;

}

are as follows:

mux_ctrl_ofs(0x54) mux_mode (0x3)

sel_input_ofs(0x914) sel_input (0x0)

pad_ctrl_ofs(0x368) pad_ctrl (0x1b0b1)

mux_ctrl_ofs(0x58) mux_mode (0x3)

pad_ctrl_ofs(0x36c) pad_ctrl (0x1b0b1)

Looking forward to your reply, thank you so much

[ShawnBai]

Ok, it seems

For DCE mode,   only 

    MX6DL_PAD_CSI0_DAT12__UART4_TXD,

    MX6DL_PAD_CSI0_DAT13__UART4_RXD,  are valid.

For DTE mode,   only

    MX6DL_PAD_CSI0_DAT12__UART4_RXD,

    MX6DL_PAD_CSI0_DAT13__UART4_TXD,  are valid.

Done.

[davidwood]

The recipe that worked for me to swap UART[0] RX and TX pins in iMX6Q:

Pin Assignments:

static iomux_v3_cfg_t mx6_iwg15m_q7_pads[] =

...

    // NOTE: must also set UART to use DTE mode!

    MX6Q_PAD_CSI0_DAT10__UART1_RXD,

    MX6Q_PAD_CSI0_DAT11__UART1_TXD,

...

}

UART initialization:

// Set DCEDTE flag to set UART into DTE mode to swap TX/RX pins

static const struct imxuart_platform_data mx6_iwg15m_q7_uart0_data __initconst = {

  .flags      = IMXUART_USE_DCEDTE

};

static inline void mx6_iwg15m_q7_init_uart(void)

{

  imx6q_add_imx_uart(0, &mx6_iwg15m_q7_uart0_data);

  imx6q_add_imx_uart(1, NULL);

  // unused

// imx6q_add_imx_uart(2, NULL);

// imx6q_add_imx_uart(3, NULL);

// imx6q_add_imx_uart(4, NULL);

}

[YixingKong]

Satoshi-san

I am looking someone internally to help now. You will see something soon.

Thanks,

Yixing

[tonyzheng]

In i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013, Charpter 64, Modem Control Signals

64.2.1.2.1 CTS - Clear To Send

Output in DCE mode. Input in DTE mode. This signal informs the remote modem that

UART is ready to receive data.

64.2.1.2.2 RTS - Request To Send

Input in DCE mode. Output in DTE mode. This signal informs UART that remote

modem is ready to receive data.

Please note that:

RX and TX signals have nothing to do with DCE&DTE mode!!!

So, RX signal is always Input and TX is always Output.

Maybe, you should modify your Excel again!

[YixingKong]

Zheng Tao, could you finish this support issue and close it as soon as possible? If you need help please contact me.

Thanks,

Yixing

[satoshishimoda]

> Please note that:

> RX and TX signals have nothing to do with DCE&DTE mode!!!

> So, RX signal is always Input and TX is always Output.

> Maybe, you should modify your Excel again!

I understood RX of "UART IP" is always input and TX of "UART IP" is always output but i.MX6 pad is not same, because DAISY bit in IOMUXC_UARTx_UART_RX DATA_SELECT_INPUT register can set to UARTx_TX_DATA.

And its description says "Route RX_DATA signal to pad when UART is in DCE mode. Route TX_DATA signal to pad when UART is in DTE mode."

Best Regards,

Satoshi Shimodau

[tonyzheng]

Hi, Shimoda

I'm sorry to reply it so late.

For example: IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT

Input Select (DAISY) Field

Selecting Pads Involved in Daisy Chain.

Route RX_DATA signal to pad when UART is in DCE mode. Route TX_DATA signal to pad when UART is in DTE mode.

00 CSI0_DATA10_ALT3 — Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA.

01 CSI0_DATA11_ALT3 — Selecting ALT3 mode of pad CSI0_DAT11 for UART1_RX_DATA.

10 SD3_DATA7_ALT1 — Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA.

11 SD3_DATA6_ALT1 — Selecting ALT1 mode of pad SD3_DAT6 for UART1_RX_DATA.

In this case, more than one pad may drive a single module input pin. When UART is in DCE mode, the UART IP block will route RX_DATA signal to pad.

But please NOTE:Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA and Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA will be invalid! Because the module pin is only RX_DATA signal.

More in deeply, UART FIFO Control Register (UARTx_UFCR) has a DCEDTE bit field as follows:

DCE/DTE mode select. Select UART as data communication equipment (DCE mode) or as data terminal

equipment (DTE mode).

0 DCE mode selected

1 DTE mode selected

When you set DCEDTE to 0, UART will be in DCE mode. Now, Daisy Chain routes RX_DATA signal to pad and there is only RX_DATA signal on input path. What you can select is 01 CSI0_DATA11_ALT3 and 11 SD3_DATA6_ALT1 for UART1_RX_DATA!!!

Now, Do you have other questions?

If any questions, welcome to discuss with me!

regards,

Tao Zheng

[satoshishimoda]

Hi Tao Zheng,

Thank you for your reply, but sorry, I have been confused yet.

> When you set DCEDTE to 0, UART will be in DCE mode. Now, Daisy Chain routes RX_DATA signal to pad and there is only RX_DATA signal on input path. What you can select is 01 CSI0_DATA11_ALT3 and 11 SD3_DATA6_ALT1 for UART1_RX_DATA!!!

In this DCE mode, what pad is assigned to UART1_TX_DATA?

And how about in DTC mode?

What pad is assigned to UART1_RX_DATA and UART1_TX_DATA?

Best Regard,

Satoshi Shimoda

[tonyzheng]

HI Satoshi,

Please take a good look at Table 64-2. UART1 External Signals in i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013, CSI0_DAT10(ALT3) and SD3_DAT7(ALT1) can be assigned to be UART1_TX_DATA!

In the DTE mode, it is similiar with DCE mode.

yours,

Tao Zheng

[YixingKong]

Tao, could you keep following this thread and reply the customer's question on 7/18? We need to clsoe this DI as soon as possible. If you, for some reason, could not continue to help this issue please let me know.

Thanks,

Yixing

xiaoli.zhang, FYI

[YixingKong]

Tao, could you keep following this thread and reply the customer's question on 7/18?

Thanks,

Yixing

[satoshishimoda]

Hi Tao Zheng,

According to your reply, same pads (CSI0_DATA11_ALT3 or11 SD3_DATA6_ALT1 for RX,  CSI0_DAT10_ALT3 or SD3_DAT7_ALT1 for TX) are used even though UART mode is DTE or DCE, right?

If it is right, I feel the following table in i.MX6: What does the DTE/DCE in i.MX6's UART do and how are RTS and CTS affected by the UARTxUFCR[DT... is wrong.

IO port	DTE mode		DCE mode
	direction	Uart IP port(internal)	direction	Uart IP port(internal)
UART_CTS_B	O	CTS_B	I	RTS_B
UART_RTS_B	I	RTS_B	O	CTS_B
UART_TXD	O	TXD	I	RXD
UART_RXD	I	RXD	O	TXD

Best Regards,

Satoshi Shimoda