i.MX6 SSI TX FIFO stuck

[philippeleduc]

Hello,

I am trying to play sound with a baremetal application. The board is using the max98355a codec. I have connected AUDMUX port 2 to port 3, and configures the SSI2 to I2S master mode. However, the TX FIFO never empties (I wrote 15 samples and waits indefinitely that the FIFO drops samples...). I don't know what's going wrong (since it freeze) and how to debug that...

Here is a dump of the SSI register (before writing to the FIFO):

SCR    : 0x00000237

SISR   : 0x00001001

SIER   : 0x00003003

STCR   : 0x000002e9

SRCR   : 0x00000280

STCCR  : 0x0000e11e

SRCCR  : 0x00040000

SFCSR  : 0x00440044

SACNT  : 0x00000000

SACADD : 0x00000000

SACDAT : 0x00000000

SATAG  : 0x00000000

STMSK  : 0x00000000

SRMSK  : 0x00000000

SACCST : 0x00000000

Here is a dump of the AUDMUX registers:

PTCR1: 0xad400800

PDCR1: 0xa000

PTCR2: 0x800

PDCR2: 0x4000

PTCR3: 0x8c400800

PDCR3: 0x2000

PTCR4: 0x800

PDCR4: 0x4000

PTCR5: 0x800

PDCR5: 0x2000

PTCR6: 0x800

PDCR6: 0x0

PTCR7: 0x800

PDCR7: 0xc000

Here is a dump of the CCM registers:

CCR:     40110ff

CCDR:    0

CSR:     38

CCSR:    100

CACRR:   0

CBCDR:   189c0

CBCMR:   b51224

CSCMR1:  f00000

CSCMR2:  2b92f06

CSCDR1:  490b00

CS1CDR:  ec102c1

CS2CDR:  7312c1

CDCDR:   33e77f92

CHSCCDR:         12090

CSCDR2:  29090

CSCDR3:  14e41

CDHIPR:  0

CLPCR:   79

CISR:    45a0000

CIMR:    ffffffff

CCOSR:   10e017f

CGPR:    fe62

CCGR0:   ffffffff

CCGR1:   ffffffff

CCGR2:   ffffffff

CCGR3:   ffffffff

CCGR4:   ffffffff

CCGR5:   ffffffff

CCGR6:   ffffffff

CMEOR:   7fffffff

Thank you in advance !

[philippeleduc]

Hi,

I found the problem! The default SSI clock root derived from the PLL3 PFD2, which was gated! I enable it in CCM_ANALOG and I get sound now!

Thank you for the support :smileyhappy:

[igorpadykov]

Hi Philippe

I think you can find SSI2 examples in

i.MX 6Series Platform SDK : Bare-metal SDK

folder /audio

Best regards

igor

[philippeleduc]

Hi,

Well I have already read and analyzed this example, and it is very similar to my code :smileyconfused:

In fact, I do not understand why the FIFO is stuck: even if I misconfigured many things, should I not get either no sound or bad sound but with an empty FIFO? (SSIEN is set, TE is set, TFEN0 is set, the WL is set to 32bits since I2S is in master mode)...

It may be related to clocks, but as you can see, every modules are enabled (CCCGRx to 0xffffffff -> the power saving will come later ! :smileygrin:)

[igorpadykov]

you should see I2S clock, also some I2S settings

are fixed, check sect. 61.8.1.4 I2S Mode IMX6DQRM

~igor