i.MX6 Qaud Ethernet PHY Link Up/Down Issue

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i.MX6 Qaud Ethernet PHY Link Up/Down Issue

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jjh2171
Contributor I

Hi, I'm Developing Custom Board using i.MX6 Quad AP.

On some board's ethernet PHY using LAN8720 from Microchips continuously toggle Link Up/Down.

Although PHY Resets using ifconfig command, Malfunction doesn't disappear.

Our Kernel Version is 4.19.35 from i.MX6 BSP Code.

Also, I tried to change and test the old Kernel that is Kernel Version of 4.1.15.

It occurs the same malfunction.

that malfunction is like the below picture.

jjh2171_0-1623206818469.png

ethernet driver continuously received Link Up/Down Event from PHY.

I check the previous question attached below.

Link: https://community.nxp.com/t5/i-MX-Processors/Toggling-up-down-ethernet-link-IMX6UL-LAN8720/m-p/12227...

it doesn't work.

Please refer to our device tree source.

I use GPIO_16 Pins to ENET_REF_CLK.

Also, I check Clock from ENET_REF_CLK(50Mhz).

FEC node :

jjh2171_1-1623207271722.png

pinctrl : 

jjh2171_2-1623207311735.png

clk-imx6q:

jjh2171_3-1623207366016.png

 

Do you have any idea to solve it?

 

Regards, Junho Jang

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Junho

 

for that issue one can recheck with oscilloscope timings described

in sect.4.12.5.2 RMII Mode Timing  i.MX 6Dual/6Quad Applications Processors for Consumer Products - Data Sheet

 

Best regards
igor

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jjh2171
Contributor I

I'll check RII Mode Timing with the oscilloscope.

But, I change GPIO16_ENET_CLK to provide RMII Clock(50Mhz) from LAN8720.

(GPR Register to IMX6Q_GPR1_ENET_CLK_SEL_PAD)

it works Well on Some Malfunction Board now.

I have to find out the cause. The reason why We generally use this schematic in other projects.

So, I'll reply to a question if have another question in this Message.

 

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