i.MX6 NAND Timing setting.

[satoshishimoda]

Hi community,

I have a question about i.MX6 GPMI and NAND boot.

Our customer want to know how m_NANDTiming of FCB is used for NAND timing setting.

And want to know the relationship between m_NANDTiming and CCM register and GPMI register if CCM register setting is added to DCD for NAND boot also.

Actually, the partner add CCM setting in DCD file to rapid NAND access because NAND access on boot sequence was slow.

Then, please see my question as following.

[Q1]

When m_NANDTiming setting is applied?

Immediately after reading FCB?

After copy DBBT to iRAM?

Or on the time start downloading a boot loader from NAND?

[Q2]

Some parameter in m_NANDTiming is set by GPMI register too.

(e.g. data setup, data hold, address setup)

Then, could you let me know which setting (m_NANDTiming or GPMI register) is used on each timing?

(e.g. boot loader => mNANDTiming, after kernel uncompression => GPMI register)

[Q3]

I think NAND timing set by m_NANDTiming is not effected even if user change CCM setting in DCD to rapid NAND access.

Because the CCM setting decides only clock period, and m_NANDTiming does not have the period setting.

Is this correct?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi, answers below.

[Q1]When m_NANDTiming setting is applied?Immediately after reading

FCB?After copy DBBT to iRAM?Or on the time start downloading a boot

loader from NAND?

A1. m_NANDTiming setting are applied immediately after reading

FCB by iROM.

[Q2]Some parameter in m_NANDTiming is set by GPMI register too.(e.g. data setup,

data hold, address setup)Then, could you let me know which setting (m_NANDTiming

or GPMI register) is used on each timing? (e.g. boot loader => mNANDTiming, after

kernel uncompression => GPMI register)

A2. I am not quite sure if I understood well question.

Yes, iROM boot loader uses mNANDTiming, however each application:

Uboot or Linux MTD NAND driver can use own GPMI settings.

[Q3]I think NAND timing set by m_NANDTiming is not effected even if user

change CCM setting in DCD to rapid NAND access.Because the CCM

setting decides only clock period, and m_NANDTiming does not have the

period setting.Is this correct?

A3. Yes,  m_NANDTiming settings do not have the period setting,

because they define one NAND data access (setup, hold times),

while DCD CCM defines (period) - that is how fast processor core accesses

to NAND. So actually CCM settings in DCD can rapid NAND access.

Best regards

chip

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