i.MX6, Linux, PCIe Configuration Read intermittently returns 0xFFs - doesn't issue PCIe transaction.

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i.MX6, Linux, PCIe Configuration Read intermittently returns 0xFFs - doesn't issue PCIe transaction.

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darkroom
Contributor I

i.MX6, U-Boot 2021.07, Poky (Yocto Project Reference Distro) 3.1.13 (dunfell).

This ONLY happens on the DualLite and the Dual, not on the Quad.

PCIe Configuration reads intermittently returns 0xFFs.

lspci dump:

root@mi-nhep:~# lspci -xxx -s 01:00.0
01:00.0 Network controller: Intel Corporation Wi-Fi 6 AX200 (rev ff)
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 8c 00
30: 00 00 00 00 c8 00 00 00 00 00 00 00 00 01 00 00
40: 10 80 02 00 c0 8e 00 10 10 0c 11 00 12 e8 45 04
50: 00 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 12 08 08 00 05 00 00 00 06 00 00 00
70: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 11 00 0f 00 00 20 00 00 00 30 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 01 d0 23 c8 08 00 00 0d
d0: 05 40 80 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have a PCIe analyzer, and the above transaction on the analyzer shows that the first PCIe transaction for this device is at Configuration register address 0x07, which corresponds to the valid data at 0x1C-0x1F above!  So, the PCIe configuration read register transactions for address 0-6 are never executed on the PCIe bus.

What could cause software to not issue a PCIe Configuration Read cycle?

The results are intermittent, in other words, sometimes it reads the whole configuration space just fine, sometimes it reads the whole configuration space as 0xFFs, and sometimes it reads only part of the configuration space as 0xFF, but it's always in a block as shown above.

Any ideas appreciated.

Best Regards,

Austin

 

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Bio_TICFSL
NXP TechSupport
NXP TechSupport

Hello,

This may be one of the errata, please check the Errata document for MX6DQCE:

https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf

Regards

 

 

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darkroom
Contributor I
Was there a particular issues in the errata that you thought this may be related to?

Thanks!

Austin
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