i.MX6 IPU di0_sync_count_sel

[sugiyamatoshihi]

Hi,

I have a question of di0_sync_count_sel bit in IPUx_DI0_GENERAL register.

It described that 'For synchronous flow error: selects synchronous flow synchronization counter in DI:'

What is is this synchronization counter? Is it one of counter #0 to #8 in DI?

If so, How to chose the counter?  IS it like, if  DISP clock would like to stop, chose counter #0, or if  Hsync would like to stop, chose counter#2?

Best Regards,

Sugiyama

[art]

Yes, the di0_sync_count_sel bit field selects between the DI counters #1 to #8.

Have a great day,
Artur

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[sugiyamatoshihi]

Hi, Artur,

Could you teach how counter # set? 

Is it below case or another?

Case1:

0000 counter is disabled

0001 counter #1 is selected
1000 counter #8 is selected

Case2:

000 Counter is disabled
001 The counter is triggered by the same trigger that triggers the displays clock.
010 The Counter is triggered by counter #1

011 The Counter is triggered by counter #2
100 The Counter is triggered by counter #3

:

101 The Counter is triggered by counter #8

Best Regards,

Sugiyama

[art]

The Case1 above is correct.

Best Regards,

Artur

[sugiyamatoshihi]

Hi, Artur,

Thank you for the answer.

I understood.

Best Regards,

Sugiyama

[b50231katsuhiro]

Hi art‌

Could you please follow-up his question?

[sugiyamatoshihi]

Hi, Artur,

Can you answer this counter # question?

Best Regards,

Sugiyama